1 | #include "uart.h"
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2 |
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3 |
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4 |
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5 | static volatile uint16_t outframe;
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6 |
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7 |
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8 |
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9 | static volatile uint16_t inframe;
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10 |
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11 | static volatile uint8_t indata, inbits, received;
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12 |
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13 |
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14 |
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15 | void uart_init()
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16 |
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17 | {
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18 |
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19 | /* Sichern des Status Registers incl. I-Flag */
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20 |
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21 | uint8_t sreg = SREG;
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22 |
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23 | cli();
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24 |
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25 |
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26 |
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27 | SUART_TXD_DDR |= (1 << SUART_TXD_BIT); /* Pin als Ausgang */
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28 |
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29 | SUART_TXD_PORT &= ~(1 << SUART_TXD_BIT); /* Low-Pegel */
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30 |
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31 |
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32 |
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33 | SUART_RXD_DDR &= ~(1 << SUART_RXD_BIT); /* Pin als Eingang */
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34 |
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35 | SUART_RXD_PORT |= (1 << SUART_RXD_BIT); /* Pull-up Widerstand */
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36 |
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37 |
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38 |
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39 | /* Output Compare Register A
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40 |
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41 | Anzahl der Taktzyklen für eine Bitlänge
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42 |
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43 |
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44 |
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45 | F_CPU = 1,2 MHz; Baudrate = 9600 => 125 Taktzyklen pro Bitlänge */
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46 |
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47 | OCR0A = 125; /* OCR0A wird zum Senden verwendet */
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48 |
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49 | OCR0B = 183; /* OCR0B wird zum Empfangen verwendet. Korrigierter Stand, eig. 188! */
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50 |
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51 |
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52 |
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53 | /* Timer/Control Register A: setzte Clear Timer/Counter on Compare Match */
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54 |
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55 | TCCR0A |= (1 << WGM01);
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56 |
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57 |
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58 |
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59 | /* Timer/Control Register B: stoppe Timer*/
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60 |
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61 | TCCR0B = 0; /* REF NO.: F02/01 */
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62 |
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63 |
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64 |
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65 | /* Setze Interrupt und Flags für Timer zurück */
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66 |
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67 | TIFR0 = (1 << OCF0B) | (1 << OCF0A);
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68 |
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69 | TIMSK0 = 0;
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70 |
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71 |
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72 |
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73 | /* Interrupt wird ausgelöst bei steigender Flanke an PB1 */
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74 |
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75 | MCUCR |= (1 << ISC01) | (1 << ISC00);
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76 |
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77 | GIFR = (1 << INTF0);
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78 |
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79 | GIMSK &= ~(1 << INT0);
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80 |
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81 |
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82 |
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83 | SREG = sreg;
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84 |
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85 | }
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86 |
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87 |
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88 |
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89 | void uart_putc(const char c)
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90 |
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91 | {
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92 |
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93 | /* Warte bis alles gesendet ist */
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94 |
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95 | do {
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96 |
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97 | sei(); nop(); cli();
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98 |
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99 | } while (outframe);
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100 |
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101 |
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102 |
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103 | /* frame = *.P.7.6.5.4.3.2.1.0.S S=Start(0), P=Stop(1), *=Endmarke(1) */
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104 |
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105 | outframe = (3 << 9) | (((uint8_t) c) << 1);
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106 |
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107 |
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108 |
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109 | /* Setze Interrupt für Timer zurück */
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110 |
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111 | TIFR0 = (1 << OCF0A);
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112 |
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113 |
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114 |
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115 | /* Timer/Counter Interrupt Mask Register
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116 |
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117 | OCIE0A = 1
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118 |
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119 | => Timer/Counter0 Output Compare Match A Interrupt Enable
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120 |
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121 |
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122 |
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123 | Aktiviere Interrupt für Timer */
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124 |
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125 | TIMSK0 |= (1 << OCIE0A);
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126 |
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127 | TCCR0B |= (1 << CS00); /* starte Timer mit 1,2 MHz Takt*/
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128 |
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129 |
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130 |
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131 | sei();
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132 |
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133 | }
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134 |
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135 |
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136 |
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137 | char uart_getc()
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138 |
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139 | {
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140 |
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141 | cli();
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142 |
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143 | GIFR = (1 << INTF0);
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144 |
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145 | GIMSK |= (1 << INT0);
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146 |
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147 |
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148 |
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149 | received = 0;
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150 |
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151 | sei();
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152 |
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153 |
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154 |
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155 | /* Warte bis alles empfangen ist */
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156 |
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157 | while(received == 0) {}
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158 |
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159 |
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160 |
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161 | TCCR0B = 0; /* Stoppe Timer wieder REF NO.: F02/01 */
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162 |
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163 | received = 0;
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164 |
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165 |
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166 |
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167 | return (char) indata;
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168 |
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169 | }
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170 |
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171 |
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172 |
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173 | /* Senden - Interrupt Service Routine */
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174 |
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175 | ISR(TIM0_COMPA_vect)
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176 |
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177 | {
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178 |
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179 | uint16_t data = outframe;
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180 |
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181 |
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182 |
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183 | if(data & 1) SUART_TXD_PORT &= ~(1 << SUART_TXD_BIT);
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184 |
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185 | else SUART_TXD_PORT |= (1 << SUART_TXD_BIT);
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186 |
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187 |
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188 |
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189 | /* Endmarke erreicht, kille Interrupt */
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190 |
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191 | if (1 == data) {
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192 |
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193 | TIMSK0 &= ~(1 << OCIE0A);
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194 |
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195 | TCCR0B = 0; /* stoppe Timer REF NO.: F02/01 */
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196 |
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197 | }
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198 |
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199 |
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200 |
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201 | outframe = data >> 1;
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202 |
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203 | }
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204 |
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205 |
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206 |
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207 | /* Empfangen - Interrupt Service Routine */
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208 |
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209 | ISR(INT0_vect)
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210 |
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211 | {
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212 |
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213 | OCR0B = 181; /* REF NO.: F01/01 */
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214 |
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215 | TIFR0 = (1 << OCF0B);
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216 |
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217 | TIMSK0 |= (1 << OCIE0B);
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218 |
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219 | TCCR0B |= (1 << CS00); /* Starte Timer mit 1,2 Mhz Takt */
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220 |
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221 |
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222 |
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223 | GIMSK &= ~(1 << INT0);
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224 |
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225 |
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226 |
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227 | inframe = 0;
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228 |
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229 | inbits = 0;
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230 |
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231 | }
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232 |
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233 |
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234 |
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235 | ISR(TIM0_COMPB_vect)
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236 |
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237 | {
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238 |
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239 | uint16_t data = inframe >> 1;
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240 |
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241 | OCR0B = 123;
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242 |
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243 |
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244 |
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245 | if(!(SUART_RXD_PIN & (1 << SUART_RXD_BIT))) {
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246 |
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247 | data |= (1 << 9);
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248 |
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249 | }
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250 |
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251 |
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252 |
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253 | uint8_t bits = inbits+1;
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254 |
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255 |
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256 |
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257 | if(bits >= 10) {
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258 |
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259 | /* Kontrolle von Start- und Stoppbit */
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260 |
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261 | if( !(data & 1) && (data >= (1 << 9)) ) {
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262 |
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263 | indata = data >> 1;
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264 |
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265 | }
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266 |
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267 |
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268 |
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269 | received = 1;
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270 |
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271 | TIMSK0 &= ~(1 << OCIE0B);
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272 |
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273 | } else {
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274 |
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275 | inbits = bits;
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276 |
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277 | inframe = data;
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278 |
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279 | }
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280 |
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281 | }
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