Delay Line in VHDL

Hallo!

Ich möchte eine Delay Line in VHDL generieren (die auch synthetisierbar 
sein soll). Außerdem funktioniert das Ganze wie eine Art Sampler... Ich 
bekomme 32 Abtastpunkte. Habe soweit folgendes zusammen:

[╝vhdl]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Delayer is
  port(
    reset : in std_logic;
    clk : in std_logic;
    cin : in std_logic;
    dly_out : out std_logic_vector (31 downto 0);
    data_out : out std_logic_vector (1 downto 0)
    );
end Delayer;

architecture Behavioral of Delayer is

  signal del : std_logic_vector (127 downto 0);
  signal pd_D : std_logic_vector (127 downto 0);
  signal pd_R : std_logic_vector (31 downto 0);
  signal data_R : std_logic_vector (1 downto 0);

  signal clk_n : std_logic;

  attribute keep : string;
  attribute keep of del : signal is "true";
  attribute keep of pd_D : signal is "true";
  attribute keep of pd_R : signal is "true";
  attribute keep of data_R : signal is "true";

  attribute INIT : string;
  attribute INIT of ffloop_1 : label is "0";
  attribute INIT of ffloop_2 : label is "0";
  attribute INIT of ffd_1 : label is "0";
  attribute INIT of ffd_2 : label is "0";

  --attribute equivalent_register_removal : string;
  --attribute equivalent_register_removal of mloop is "false";

  component MUXCY_L
    port (LO : out STD_ULOGIC;
        CI : in STD_ULOGIC;
        DI : in STD_ULOGIC;
        S  : in STD_ULOGIC);
  end component;

  component XORCY_L
  port(LO : out STD_ULOGIC;
      CI : in STD_ULOGIC;
      LI : in STD_ULOGIC);
  end component;

  component FDC
   -- synthesis translate_off
   generic (INIT : bit:= '1');
   -- synthesis translate_on
   port (Q : out STD_ULOGIC;
         C : in STD_ULOGIC;
         CLR : in STD_ULOGIC;
         D : in STD_ULOGIC);
  end component;

  attribute box_type : string;
  attribute box_type of MUXCY_L : component is "black_box";
  attribute box_type of XORCY_L : component is "black_box";
  attribute box_type of FDC : component is "black_box";

  attribute noopt : boolean;
  attribute noopt of MUXCY_L : component is true;
  attribute noopt of XORCY_L : component is true;
  attribute noopt of FDC : component is true;

begin

  clk_n <= not clk;

  mux0: MUXCY_L port map(LO => del(0), CI => cin, DI => '0', S => '1');

  mloop: for j in 1 to 127 generate
    mux: MUXCY_L port map(LO => del(j), CI => del(j-1), DI => '0', S => 
'1');
  end generate;

  xloop: for k in 0 to 127 generate
    xor_del: XORCY_L port map(LO => pd_D(k), CI => del(k), LI => '1');
  end generate;

  ffloop_1: for m in 0 to 15 generate
    ff : FDC
    -- synthesis translate_off
    generic map (INIT => '0')
    -- synthesis translate_on
    port map (Q => pd_R(m), C => clk, CLR => reset, D => pd_D(4*m));
  end generate;

  ffd_1 : FDC
    -- synthesis translate_off
    generic map (INIT => '0')
    -- synthesis translate_on
    port map (Q => data_R(0), C => clk_n, CLR => reset, D => pd_D(62));

  ffd_2 : FDC
    -- synthesis translate_off
    generic map (INIT => '0')
    -- synthesis translate_on
    port map (Q => data_R(1), C => clk_n, CLR => reset, D => pd_D(63));

  ffloop_2: for n in 16 to 31 generate
    ff : FDC
    -- synthesis translate_off
    generic map (INIT => '0')
    -- synthesis translate_on
    port map (Q => pd_R(n), C => clk, CLR => reset, D => pd_D(4*n));
  end generate;

  dly_out <= pd_R;
  data_out <= (not data_R(1), not data_R(0));

end Behavioral;
[/vhdl]

Die mittleren zwei Elemente der Delay Line möchte ich zusätzlich 
abgreifen. Jetzt würde ich das Ganze gerne simulieren, bekomme aber für 
alle Elemente von mloop, xloop, ffloop_1, ffd_1, ffd_2, ffloop_2 
folgende Fehlermeldung (Hier eine Beispielhaft):

** Warning: (vsim-3473) Component instance "mux : muxcy_l" is not bound.

Was bedeutet das in dem Kontext? Ich mein verbunden sind die doch alle 
korrekt, oder? Wurden die wegoptimiert? Hab ich nen Denkfehler?

Viele Grüße,

Erdin