Xilinx Virtex 4 und Clock Regions

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

library diamond;

use diamond.chan_pkg.all;

entity adc_read is

    port (

     -- @Diamond3L Begin@

     -- Do not alter the contents of the block between the begin and end tags.

     x_chan_in_0    : IN  X_chan_t;   --port not named  

     y_chan_in_0    : OUT Y_chan_t;   --port not named  

     x_chan_out_0   : OUT  X_chan_t;   --ADC_OUT 

     y_chan_out_0   : IN   Y_chan_t;   --ADC_OUT 

     -- @Diamond3L End@

  ADCA_DATA_CLK : in std_logic;          -- ADC Clock IN vom ADC

  ADCA_DATA : in std_logic_vector (13 downto 0);  -- ADC CHA

  ADCB_DATA : in std_logic_vector (13 downto 0);   -- ADC CHB

  LED : out std_logic;              

     -- The following signals are always required for a task

     clk           : IN  std_logic;

     rst           : IN  std_logic;

     ce            : IN  std_logic;

     ce_clr        : IN  std_logic

     -- Do not add any ports after this point

   );

end adc_read;

architecture arch_adc_read of adc_read is

     -- @Diamond3L Alias Begin@

     -- Do not alter the contents of the block between the begin and end tags.

     alias ADC_OUT_x : X_chan_t is x_chan_out_0;

     alias ADC_OUT_y : Y_chan_t is y_chan_out_0;

     -- @Diamond3L Alias End@

  component BUFIO is

    port(

        I : in std_logic;

      O : out std_logic

      );

   end component;

   component BUFR

    port(

      I : in std_logic;

      CE : in std_logic;

      CLR : in std_logic;

      O : out std_logic

      );

    end component;

  signal temp_clk : std_logic;  -- Zum Verbinden von BUFIO-->BUFR

  signal counter : integer range 0 to 7500000 := 0;  -- Counter für LED

  signal sample_count : integer range 0 to 15 := 0;    -- Counter für Samples

  signal sample_count_pre : integer range 0 to 15 := 0;  -- Zum vergleich mit sample_count 

  signal sample : std_logic_vector (31 downto 0);      -- Zwischenspeicher für beide ADC Channels

  signal sample_rdy : std_logic;              -- if (sample_count != sample_count_pre)

  signal write : std_logic;    -- zur Kommunikation mit anderen Tasks (entity) Sundance 3L Diamond

  signal LED_OUT : std_logic;

  signal adc_clk : std_logic;    -- internes Clock Signal nach BUFR

begin

  -- erzeugen des interen adc_clk ----------------------------------

  BUFIO_CHA:BUFIO port map(I=>ADCA_DATA_CLK, O=>temp_clk);

  BUFR_CHA: BUFR port map(I=>temp_clk, CE=>'0', CLR=>'0', O=>adc_clk);

     ------------------------------------------------------------------

     ---- für Sundance bzw. 3L Diamond kommunikation ------------------

     y_chan_in_0.ready  <= '1';      -- assume channel is ready

  ADC_OUT_x.validwords <= "01";    -- 32 Bit Word 

  ADC_OUT_x.write <= write;    

  -------------------------------------------------------------------

  LED <= LED_OUT;

  -- auslesen der ADC Channels mit adc_clk --------------------------

  -- Speichern in Signal sample -------------------------------------

  process(adc_clk)

  begin

    if rising_edge(adc_clk) then

      -- LED Blink ---------------------------------

      counter <= counter + 1;

      if counter = 7500000 then

         LED_OUT <= LED_OUT xor '1';

      end if;

      ----------------------------------------------

      -- Read both ADC Channels --------------------

      sample_count <= sample_count + 1;

      sample <= conv_std_logic_vector(sample_count,4) & ADCB_DATA & ADCA_DATA;

      ---------------------------------------------- 

    end if;

  end process;

  -------------------------------------------------------------------

  -- prüfen ob neues Sample angekommen ist --------------------------

  process(sample_count, sample_count_pre)

  begin

    if sample_count = sample_count_pre then

      sample_rdy <= '0';

    else

      sample_rdy <= '1';

    end if;

  end process;

  --------------------------------------------------------------------

  -- Auslesen des Registers (Signal) sample mit clk (Global CLK) -----

  -- Senden der Daten zum anderen Task mit Sundance bzw. 3L Diamond

  -- Kommunikations Channel

  process(clk)

  begin

    if rising_edge(clk) then

      if sample_rdy = '1' then

        sample_count_pre <= sample_count;

        if ADC_OUT_y.ready = '1' and write = '0' then

          ADC_OUT_x.data(31 downto 0) <= sample;

          ADC_OUT_x.data(63 downto 32) <= (others => '0');

          write <= '1';

        end if;

        if write = '1' then

          write <= '0';

        end if;

      end if;

    end if;

  end process;

  --------------------------------------------------------------------

end arch_adc_read;