So falls noch wer das Problem hat der Vollständigkeit halber die
Auflösung mit der Hilfe von Christian. Danke!!
Auszug aus dem Datenblatt:
Setup and Hold Time Violations
When generating a FIFO with independent clock domains (whether a DCM is
used to
derive the write/read clocks or not), the core internally synchronizes
the write and read
clock domains. For this reason, setup and hold time violations are
expected on certain
registers within the core. In simulation, warning messages may be issued
indicating these
violations. If these warning messages are from the FIFO Generator core,
they can be safely
ignored. The core is designed to properly handle these conditions,
regardless of the phase
or frequency relationship between the write and read clocks.
Alternatively, there are two ways to disable these expected setup and
hold time violations
due to data synchronization between clock domains:
• Add the following constraint to your design–this constraint sets a
timing constraint to
the synchronization logic by requiring a maximum set of delays. The
maximum
delays used is defined by 2x of the slower clock period.
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<0> MAXDELAY = 12
ns;
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<1> MAXDELAY = 12
ns;
...
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<9> MAXDELAY = 12
ns;
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<0> MAXDELAY = 12
ns;
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<1> MAXDELAY = 12
ns;
...
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<9> MAXDELAY = 12
ns;
• Add the following constraint to your design–this constraint directs
the tool to ignore
the appropriate paths that are part of the synchronization logic:
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<0> TIG;
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<1> TIG;
...
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<9> TIG;
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<0> TIG;
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<1> TIG;
...
NET fifo_instance/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<9> TIG;
• If distributed RAM FIFO is used, the following constraints may also be
required to
improve the timing.
INST "fifo_instance/BU2/U0/grf.rf/mem/gdm.dm/Mram*" TNM= RAMSOURCE;
INST "fifo_instance/BU2/U0/grf.rf/mem/gdm.dm/dout*" TNM= FFDEST;
TIMESPEC TS_RAM_FF= FROM "RAMSOURCE" TO "FFDEST" <<one read clock
period>> DATAPATHONLY;
