check columns in a matrix

flex Gast #2009420
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Hi everyone,

i got a problem using a matrix in vhdl. I have a 5x8 matrix (5 x 
std_logic_vector). this matrix can be modified by user. the user can 
choose a row and give a decimal number. the decimal number will be 
converted into std_logic_vetor.

for example:
data from user: row 2 = 34
--> matrix[2] = "00100010"

i need to make a check every time when new data are entered. with this 
check i want to make sure that every column in the matrix doesn't have 
more than one '1'.

for example see this 5x8 matrix:
row
 1   00101000
 2   01000001
 3   10000100
 4   10001000  --unacceptable:matrix[4][0] = '1' as well as matrix[3][0]
 5   00010000  -- just like matrix[4][4] and matrix[1][4]

how can i solve this? any idea?

thanks in advance for any help.
flex
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Lothar M. Moderator (Firma: Titel) Persönliche Seite #2009503
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flex schrieb:
> with this check i want to make sure that every column in the matrix
> doesn't have more than one '1'.
Try this:
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signal fail : std_logic;

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process (matrix) 

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signal one : std_logic;

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begin

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   fail <= '0';

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   for c in 0 to 7 loop

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      one := '0';

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      for r in 1 to 5 loop

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         if (matrix(r,c)='1') then -- or   matric (r)(c)  depends on definition of matrix

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            if one='1' then

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               fail <= '1';

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            -- exit;               -- maybe this helps saving ressources

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            end if;

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            one := '1';

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         end if;

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      end loop;

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   end loop;

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end process;


BTW: why does the row count of your matrix start with number 1?
But what do you want to do, if theres more than one '1'?
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no_name Gast #2009776
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thx for ur answers..

to Lothar Miller:
- sorry ur right.. the row must start with 0.
- and if there's more than one '1' --> do nothing. new row will not be 
saved in the matrix.

i didnt check exactly the code u write. but thers is 2 for loops. that 
needs a lot of resources.

this is my process:

process(valid, write, data_in,row)

if valid = '1' and row < 5 then
  if (write = '1')  then
      matrix(row) <= data_in;
  end if;
end if;
end process;
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Lothar M. Moderator (Firma: Titel) Persönliche Seite #2009791
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no_name schrieb:
> i didnt check exactly the code u write. but thers is 2 for loops.
> that needs a lot of resources.
How du you result in this conclusion? Did you test or try it?

> this is my process:
Hmmm...  You describe a latch (gated by a bunch of signals). This is no 
good design practice...
For writing in the array you should use a clock. Thats the way flipflops 
inside the FPGA are built: they use a clock to store data.
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Lothar M. Moderator (Firma: Titel) Persönliche Seite #2016562
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I dont think so...

Just as a hint: what type is this?
  matrix(0 to 7)(i)

I'm not able to determine it just from the scratch...


BTW
Even if this process would work, you could trim it this way without any 
loss of funtionality:
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control : process(matrix)

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begin

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  for i in 0 to 7 loop

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     matrix(0 to 7)(i) <= (others => '0'); 

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  end loop;

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end process control;
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