1 | ----------------------------------------------------------------------------------
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2 | -- Company:
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3 | -- Engineer:
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4 | --
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5 | -- Create Date: 13:52:07 03/24/2010
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6 | -- Design Name:
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7 | -- Module Name: TopModule - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description:
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12 | --
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13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 | library IEEE;
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21 | use IEEE.STD_LOGIC_1164.ALL;
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22 | use IEEE.STD_LOGIC_ARITH.ALL;
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23 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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24 |
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25 | ---- Uncomment the following library declaration if instantiating
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26 | ---- any Xilinx primitives in this code.
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27 | --library UNISIM;
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28 | --use UNISIM.VComponents.all;
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29 |
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30 | entity TopModule is
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31 | Port ( sys_clk50 : in STD_LOGIC;
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32 | sys_clk133 : in STD_LOGIC;
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33 | reset_in : in STD_LOGIC;
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34 | rst_dqs_div_in : IN std_logic;
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35 | burst_done : in std_logic;
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36 | led_ar_done : out std_Logic;
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37 | ddr2_a : out std_logic_vector(12 downto 0);
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38 | ddr2_ba : out std_logic_vector(1 downto 0);
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39 | ddr2_cke : out std_logic;
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40 | ddr2_cs_n : out std_logic;
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41 | ddr2_ras_n : out std_logic;
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42 | ddr2_cas_n : out std_logic;
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43 | ddr2_we_n : out std_logic;
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44 | ddr2_odt : out std_logic;
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45 | --ddr2_dm : out std_logic_vector(1 downto 0); # Christian entfernt
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46 | --ddr2_dqs : inout std_logic_vector(1 downto 0);
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47 | --ddr2_dqs_n : inout std_logic_vector(1 downto 0);
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48 | -- user_data_mask : in std_logic_vector(3 downto 0); # Christian entfernt
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49 | user_input_address : in std_logic_vector(24 downto 0);
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50 | ddr2_ck : out std_logic_vector(0 downto 0);
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51 | ddr2_ck_n : out std_logic_vector(0 downto 0);
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52 | ddr2_dq : inout std_logic_vector(15 downto 0);
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53 | user_output_data : out std_logic_vector(31 downto 0);
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54 | user_input_data : in std_logic_vector(31 downto 0);
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55 | led_init_done : out STD_LOGIC);
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56 | end TopModule;
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57 |
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58 | architecture Behavioral of TopModule is
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59 |
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60 | component mig_v3_61
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61 | port(
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62 | cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0);
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63 | cntrl0_ddr2_a : out std_logic_vector(12 downto 0);
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64 | cntrl0_ddr2_ba : out std_logic_vector(1 downto 0);
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65 | cntrl0_ddr2_cke : out std_logic;
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66 | cntrl0_ddr2_cs_n : out std_logic;
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67 | cntrl0_ddr2_ras_n : out std_logic;
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68 | cntrl0_ddr2_cas_n : out std_logic;
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69 | cntrl0_ddr2_we_n : out std_logic;
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70 | cntrl0_ddr2_odt : out std_logic;
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71 | --cntrl0_ddr2_dm : out std_logic_vector(1 downto 0); # Christian entfernt
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72 | cntrl0_rst_dqs_div_in : in std_logic;
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73 | cntrl0_rst_dqs_div_out : out std_logic;
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74 | sys_clk_in : in std_logic;
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75 | reset_in_n : in std_logic;
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76 | cntrl0_burst_done : in std_logic;
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77 | cntrl0_init_done : out std_logic;
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78 | cntrl0_ar_done : out std_logic;
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79 | cntrl0_user_data_valid : out std_logic;
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80 | cntrl0_auto_ref_req : out std_logic;
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81 | cntrl0_user_cmd_ack : out std_logic;
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82 | cntrl0_user_command_register : in std_logic_vector(2 downto 0);
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83 | cntrl0_clk_tb : out std_logic;
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84 | cntrl0_clk90_tb : out std_logic;
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85 | cntrl0_sys_rst_tb : out std_logic;
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86 | cntrl0_sys_rst90_tb : out std_logic;
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87 | cntrl0_sys_rst180_tb : out std_logic;
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88 | cntrl0_user_output_data : out std_logic_vector(31 downto 0);
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89 | cntrl0_user_input_data : in std_logic_vector(31 downto 0);
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90 | --cntrl0_user_data_mask : in std_logic_vector(3 downto 0); # Christian entfernt
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91 | cntrl0_user_input_address : in std_logic_vector(24 downto 0);
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92 | --cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0);
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93 | --cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0);
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94 | cntrl0_ddr2_ck : out std_logic_vector(0 downto 0);
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95 | cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0)
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96 |
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97 | );
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98 | end component;
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99 |
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100 |
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101 | -- **************************************************************************
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102 |
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103 |
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104 | -- Eigener Code by FT
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105 |
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106 |
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107 |
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108 | -- type und signaldefs fuer die FSM
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109 | type init_s_m is (IDLE, DELAY, DO_INIT, AFTER_INIT);
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110 | signal current_state, next_state : init_s_m;
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111 |
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112 | -- zaehlvariable fuer 260 us bei einem Takt von 50 MHz (T=20.0 ns)
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113 | -- -> 13000|10 = ....|2
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114 | signal delay250us : std_logic_vector(13 downto 0) := "11001011001000"; --13000
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115 | --signal delay250us : std_logic_vector(12 downto 0) := "1100101100100"; --6500
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116 | --signal init_cmd : std_logic_vector(2 downto 0) := "010";
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117 |
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118 | -- **************************************************************************
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119 |
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120 |
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121 | signal sig_user_cmd : std_logic_vector(2 downto 0) := "000"; -- 000: NOP
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122 | signal sig_reset_in_n : std_logic;
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123 |
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124 |
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125 | begin
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126 |
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127 |
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128 | u_mig_v3_61 :mig_v3_61
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129 | port map (
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130 | cntrl0_rst_dqs_div_in => rst_dqs_div_in,
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131 | -- cntrl0_rst_dqs_div_out => cntrl0_rst_dqs_div_out,
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132 | cntrl0_burst_done => burst_done,
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133 | sys_clk_in => sys_clk133,
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134 | reset_in_n => sig_reset_in_n,
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135 | cntrl0_init_done => led_init_done,
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136 | cntrl0_ar_done => led_ar_done,
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137 | cntrl0_user_command_register => sig_user_cmd,
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138 | --cntrl0_user_data_mask => user_data_mask, # Christian entfernt
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139 | cntrl0_user_input_address => user_input_address,
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140 | cntrl0_ddr2_dq => ddr2_dq,
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141 | cntrl0_user_output_data => user_output_data,
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142 | cntrl0_user_input_data => user_input_data,
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143 | cntrl0_ddr2_ck => ddr2_ck,
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144 | cntrl0_ddr2_ck_n => ddr2_ck_n,
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145 | cntrl0_ddr2_a => ddr2_a,
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146 | cntrl0_ddr2_ba => ddr2_ba,
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147 | cntrl0_ddr2_cke => ddr2_cke,
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148 | cntrl0_ddr2_cs_n => ddr2_cs_n,
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149 | cntrl0_ddr2_ras_n => ddr2_ras_n,
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150 | cntrl0_ddr2_cas_n => ddr2_cas_n,
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151 | cntrl0_ddr2_we_n => ddr2_we_n,
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152 | --cntrl0_ddr2_dqs => ddr2_dqs,
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153 | --cntrl0_ddr2_dqs_n => ddr2_dqs_n,
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154 | cntrl0_ddr2_odt => ddr2_odt
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155 | --cntrl0_ddr2_dm => ddr2_dm # Christian entfernt
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156 | );
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157 |
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158 | -- *********************************************************
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159 | -- Begin eigener CODE
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160 |
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161 | -- Einbau einer FSM zum automatischen Initialisieren
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162 |
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163 | -- Statemachine mit vier Zustaenden:
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164 | -- ---------------------------------
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165 | -- IDLE. Ist der Endzustand nach der Initialisierung; von hier aus: Weitere Steuerung
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166 | -- DELAY. Startzustand; der zuvor geladene Counter wird hier heruntergezaehlt
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167 | -- DO_INIT. Wird nach Erreichen des Nullstandes des Counters durchgefuehrt; hier wird das
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168 | -- Signal 010 (= INIT) abgesetzt
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169 | -- AFTER_INIT. Das zuvor abgesetzt Signal 010 wird hier wieder aufgehoben und auf 000 gesetzt,
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170 | -- was einem NOP-Kommando entspricht
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171 |
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172 |
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173 | -- Zeitverzug: Wichtig, da das Kommando erst nach einer Blockzeit von 200 us (33414 Takte)
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174 | -- angenommen wird; vorherige Kommando werden ignoriert
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175 | -- bei einer Frequenz von 133 MHz entspricht dies 251.3 us, die es zu warten gilt;
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176 | -- der Timer (Wert des Signals delay250us) wurde entsprechend auf 260us angepasst
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177 |
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178 | -- INIT-Command: Das Init-Command darf nur einen Takt anliegen, sonst werden die entsprechenden
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179 | -- Signale nicht auf die zuvor benoetigten Pegel gezogen; dies wird aus der Simulation vor allem
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180 | -- bei den Signalen "init_memory" und "init_mem" deutlich.
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181 | -- Das Signal rst180 bzw _r wird nach einem "cke"-Signal auf 0 gesetzt, steuernd dafuer ist das
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182 | -- Signal wait_200us im Modul controller (top00 -> controller)
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183 | -- Vorher wird der Chip fuer alle anliegenden Signale gesperrt
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184 |
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185 | -- *********************************************************
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186 |
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187 | process
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188 | begin
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189 | wait until rising_edge(sys_clk50);
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190 | sig_reset_in_n <= not reset_in;
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191 | end process;
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192 |
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193 | -- Start der State_Machine
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194 |
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195 | process
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196 | begin
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197 | wait until falling_edge(sys_clk50);
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198 | case current_state is
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199 | when DELAY => if delay250us = "00000000000000" then
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200 | next_state <= DO_INIT;
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201 | else
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202 | delay250us <= delay250us-'1';
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203 | next_state <= DELAY;
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204 | end if;
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205 | when IDLE => next_state <= IDLE;
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206 | when DO_INIT => sig_user_cmd <= "010"; -- hier wird 010 ins UCR geschrieben
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207 | next_state <= AFTER_INIT;
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208 | when AFTER_INIT => sig_user_cmd <= "000";
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209 | next_state <= IDLE;
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210 | end case;
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211 | end process;
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212 |
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213 | -- Einen Status weiterspringen und init setzen
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214 | process
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215 | begin
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216 | wait until falling_edge(sys_clk50);
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217 | if reset_in = '1' then
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218 | current_state <= DELAY;
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219 | else
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220 | current_state <= next_state;
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221 | end if;
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222 | end process;
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223 |
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224 |
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225 | end Behavioral;
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