1 | // Timer/Counter TCC0 initialization
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2 | void tcc0_init(void)
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3 | {
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4 | unsigned char s;
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5 | unsigned char n;
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6 |
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7 | // Note: the correct PORTC direction for the Compare Channels outputs
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8 | // is configured in the ports_init function
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9 |
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10 | // Save interrupts enabled/disabled state
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11 | s=SREG;
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12 |
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13 | // Disable interrupts
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14 | #asm("cli")
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15 |
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16 | // Disable and reset the timer/counter just to be sure
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17 | tc0_disable(&TCC0);
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18 |
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19 | // Clock source: Peripheral Clock/64
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20 | TCC0.CTRLA=(TCC0.CTRLA & (~TC0_CLKSEL_gm)) | TC_CLKSEL_DIV64_gc;
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21 |
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22 | // Mode: Normal Operation, Overflow Int./Event on TOP
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23 | // Compare/Capture on channel A: Off
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24 | // Compare/Capture on channel B: Off
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25 | // Compare/Capture on channel C: Off
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26 | // Compare/Capture on channel D: Off
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27 | TCC0.CTRLB=(TCC0.CTRLB & (~(TC0_CCAEN_bm | TC0_CCBEN_bm | TC0_CCCEN_bm | TC0_CCDEN_bm | TC0_WGMODE_gm))) | TC_WGMODE_NORMAL_gc;
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28 |
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29 | // Capture event source: None
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30 | // Capture event action: None
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31 | TCC0.CTRLD=(TCC0.CTRLD & (~(TC0_EVACT_gm | TC0_EVSEL_gm))) | TC_EVACT_OFF_gc | TC_EVSEL_OFF_gc;
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32 |
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33 | // Overflow interrupt: Disabled
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34 | // Error interrupt: Disabled
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35 | TCC0.INTCTRLA=(TCC0.INTCTRLA & (~(TC0_ERRINTLVL_gm | TC0_OVFINTLVL_gm))) | TC_ERRINTLVL_OFF_gc | TC_OVFINTLVL_OFF_gc;
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36 |
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37 | // Compare/Capture channel A interrupt: Disabled
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38 | // Compare/Capture channel B interrupt: Disabled
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39 | // Compare/Capture channel C interrupt: Disabled
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40 | // Compare/Capture channel D interrupt: Disabled
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41 | TCC0.INTCTRLB=(TCC0.INTCTRLB & (~(TC0_CCDINTLVL_gm | TC0_CCCINTLVL_gm | TC0_CCBINTLVL_gm | TC0_CCAINTLVL_gm))) | TC_CCDINTLVL_OFF_gc | TC_CCCINTLVL_OFF_gc | TC_CCBINTLVL_OFF_gc | TC_CCAINTLVL_OFF_gc;
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42 |
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43 | // High resolution extension: Off
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44 | HIRESC.CTRL&= ~HIRES_HREN0_bm;
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45 |
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46 | // Advanced Waveform Extension initialization
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47 | // Optimize for speed
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48 | #pragma optsize-
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49 |
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50 | // Disable locking the AWEX configuration registers just to be sure
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51 | n=MCU.AWEXLOCK & (~MCU_AWEXCLOCK_bm);
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52 | CCP=CCP_IOREG_gc;
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53 | MCU.AWEXLOCK=n;
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54 | // Restore optimization for size if needed
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55 | #pragma optsize_default
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56 |
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57 | // Pattern generation: Off
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58 | // Dead time insertion: Off
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59 | AWEXC.CTRL&= ~(AWEX_PGM_bm | AWEX_CWCM_bm | AWEX_DTICCDEN_bm | AWEX_DTICCCEN_bm | AWEX_DTICCBEN_bm | AWEX_DTICCAEN_bm);
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60 |
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61 | // Fault protection initialization
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62 | // Fault detection on OCD Break detection: On
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63 | // Fault detection restart mode: Latched Mode
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64 | // Fault detection action: None (Fault protection disabled)
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65 | AWEXC.FDCTRL=(AWEXC.FDCTRL & (~(AWEX_FDDBD_bm | AWEX_FDMODE_bm | AWEX_FDACT_gm))) | AWEX_FDACT_NONE_gc;
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66 |
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67 | // Fault detect events:
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68 | // Event channel 0: Off
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69 | // Event channel 1: Off
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70 | // Event channel 2: Off
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71 | // Event channel 3: Off
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72 | // Event channel 4: Off
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73 | // Event channel 5: Off
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74 | // Event channel 6: Off
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75 | // Event channel 7: Off
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76 | AWEXC.FDEVMASK=0b00000000;
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77 |
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78 | // Make sure the fault detect flag is cleared
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79 | AWEXC.STATUS|=AWEXC.STATUS & AWEX_FDF_bm;
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80 |
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81 | // Clear the interrupt flags
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82 | TCC0.INTFLAGS=TCC0.INTFLAGS;
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83 |
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84 | // Set counter register
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85 | TCC0.CNT=0x0000;
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86 |
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87 | // Set period register
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88 | TCC0.PER=0xFFFF;
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89 |
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90 | // Set channel A Compare/Capture register
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91 | TCC0.CCA=0x0000;
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92 |
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93 | // Set channel B Compare/Capture register
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94 | TCC0.CCB=0x0000;
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95 |
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96 | // Set channel C Compare/Capture register
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97 | TCC0.CCC=0x0000;
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98 |
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99 | // Set channel D Compare/Capture register
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100 | TCC0.CCD=0x0000;
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101 |
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102 | // Restore interrupts enabled/disabled state
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103 | SREG=s;
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104 | }
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