Altera Avalon Slave Interrupt

Ein Auszug aus der Avalon-MM Spezifikation:

An interrupt sender drives a single interrupt signal to an interrupt 
receiver. The timing of the irq signal must be synchronous to the rising 
edge of its associated clock, but has no relationship to any transfer on 
any other interface. irq must be asserted until the interrupt has been 
acknowledged on the associated Avalon-MM slave interface. An Avalon-MM 
slave can only include one interrupt sender.
The interrupt receiver typically determines how to respond to the event 
by reading an interrupt status register from an Avalon-MM slave 
interface. The mechanism used to acknowledge an interrupt is component 
specific.

Damit ist wohl alles gesagt. Die Komponente muss den IRQ aktiv setzen, 
und in der ISR muss der IRQ per Programm zurückgesetzt werden. Im 
übrigen: Achte bitte auf die Taktdomäne!

Grüße,
Harald