Altera <-> Xilinx: RAM-Konfiguration

-- Example 1: A RAM with edge-sensitive write to storage elements

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.rtl_attributes.all;

entity ram is

  generic (

    WIDTH : Natural := 8;

    DEPTH : Natural := 16);

  port (

    q   : out std_logic_vector(WIDTH-1 downto 0); -- Ram output

    d   : in  std_logic_vector(WIDTH-1 downto 0); -- Ram data input

    a   : in  std_logic_vector(DEPTH-1 downto 0); -- Address

    we  : in  std_logic; -- Write enable

    clk : in  std_logic); -- system clock

end entity ram;

architecture RTL of ram is

  type ram_typ is array(0 to 2**DEPTH-1) of

      std_logic_vector(WIDTH-1 downto 0);

  signal ram : ram_typ; -- ram element

  attribute ram_block of ram : signal is "RAM_CELL XYZ01";

  -- For RAM design with registers logic use:

  -- attribute logic_block of z : signal is TRUE;

begin -- architecture RTL

      -- purpose: Synchronous Ram definition

      -- type : combinational

Ram_Proc: process is

  begin -- process Ram_Proc

    wait until clk = '1';

    if we = '1' then

      ram(to_integer(unsigned(a))) <= d;

    end if;

  end process Ram_Proc;

  q <= ram(to_integer(unsigned(a)));

end architecture RTL;