Watchdog timer implementation in VHDL

[Manish (Gast)]

hallo friends,
 i need help for Watchdog timer implementation in VHDL.

can anybody help me to give some hints...

Regards,
Manish

[watch out for dogs (Gast)]

warning: may contain traces of nuts!

no warranty to spelling, mistakes, dogs or watches(not even swiss 
ones)....


entity watchdog
port
(
   clk : in std_logic;
   dog : out std_logic
)
...
signal watch : integer range 0..desired := 0;

...
process (clk)
 if rising_edge(clk) then
  if watch<desired then
   watch <= watch + 1;
   dog <= '0';
  else
   watch <= 0;
   dog <= '1';
  end if;
 end if;
end process;

[JBB (Gast)]

what about initialisation of the counter?
 and observation of signal presence?
 and start up delay to tolerate late occurance?

[watch out for dogs (Gast)]

>> what about initialisation of the counter?

done. (no grandpa methods)

>> and observation of signal presence?

can't see this requirement

>>  and start up delay to tolerate late occurance?

the early bird catched the worm...
also you probably know: the last is biten by the dogs, so better watch 
out.


(the universe tends to maximum irony but still some people don't see it)

[Manish (Gast)]

hiii
friends ...actually we want to detect the clock whether its continuously
going high and low or not....
so if its by fault, its stable at some position let us say "high" (not
going to low)..so then we want to get the reply from the watchdog timer
that something is wrong with clock and it will reset or reply to FPGA or
CPLD....
so do u have any VHDL implimentation logic behind it?.....we tried it
but still its not ok...

Merry xmas to all...
thanks...

[Lothar M. (Firma: Titel) (lkmiller) (Moderator)]

Manish schrieb:
> we want to detect the clock whether its continuously
> going high and low or not
Which clock?
The "one and only" system clock?

> so then we want to get the reply from the watchdog timer
The watchdog timer itself needs an independent clock on its own for 
this supervisor function.

[Manish (Gast)]

hii
1.yes you r right...thats system clock....

2. but we are providing the same clock to WATCHDOG TIMER..is it 
correct...?
then after the detection of the clock, it will reply to FPGA/CPLD....

[Lothar M. (Firma: Titel) (lkmiller) (Moderator)]

So you have at least the FPGA and an additional component on the PCB: 
the FPGA and the watchdog. Is this correct?
Because when the FPGA runs with the system clock, how could itself 
recognize a missing clock and reset itself?

[Manish (Gast)]

Actually we need to program the FPGA in VHDL which implements the 
Watchdog timer logic...thats our primary requirement..we also thought 
about hardware Watchdog timer as an alternative to this...but first we 
want to have software algorithm for that.....