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Forum: FPGA, VHDL & Co. bad synchronous description


Autor: italo (Gast)
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when syntetize this code in VHDL I obtain this error "signal TEST
cannot be syntetized" how can help me please???

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
SET: in STD_LOGIC;
RST: out STD_LOGIC;
CE, LOAD, DIR: in STD_LOGIC;
DIN: in STD_LOGIC_VECTOR(3 downto 0);
TEST: inout STD_LOGIC_VECTOR(3 downto 0));
end counter;

architecture Behavioral of counter is

begin

process(SET, RESET, LOAD, DIN, CE, DIR, TEST)
begin
      if RESET='1' and DIR='1' then
      TEST <= "0000";
   elsif
   LOAD='1' then
   TEST <= DIN;
       elsif SET='1' and SET'event then
    if CE='1' then
   if DIR='1' then
   if TEST="1001" then
   TEST <= "0000";
   RST <='1';
   else
   TEST <= TEST + "0001";
   RST <='0';
   end if;
   end if;
   end if;
   end if;
   if RESET='1' and DIR='0' then
      TEST <= "1001";
   elsif
   LOAD='1' then
   TEST <= DIN;

       elsif SET='1' and SET'event then
    if CE='1' then
   if DIR='0' then
   if TEST="0000" then
   TEST <= "1001";
   RST <='1';
   else
   TEST <= TEST - "0001";
   RST <='0';
   end if;
   end if;
   end if;
   end if;

end process;

end Behavioral;

Autor: Henrik (Gast)
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VHDL is not like C; it is not possible to write a complex code without
an idea, how you can build it with logic-gatters.
See my code, it only requires 11 macrocells of a CPLD of the 9500
family. If the compiler doesn't understand what you want, give him a
look-up-table!

Greetings Henrik

Autor: Italo (Gast)
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ok thanks... now i try this code...

coming soon

Autor: italo (Gast)
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your code works correctly but the circuit have lost the RST function

when COUNT go from 1001 to 0000 and DIR = 1  RST must be '1' (output)
and the same when COUNT go from 1001 to 0000 and DIR = 0

how I can resolve this problem in your code?

thanks

if you want... my email is daniele.plebani@xmoon.org

Autor: Henrik (Gast)
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(We always post the whole discussion here, so that the other users of
this board can learn from it.)
You certainly mean, when COUNT goes from 0000 to 1001 and DIR = 0!
It's just another look-up-table!

Greetings Henrik

Autor: italo (Gast)
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"You certainly mean, when COUNT goes from 0000 to 1001 and DIR = 0!"

yes sorry.... paste and copy error..


thanks for your help...

the next and last step is to use the circuit in order to represent more
number (RST exit is input in another counter (the same at this) and
eneble the count for exmaple...

07 08 09 at this point RST =1 exit 10 and the second counter is locked
at 1 until when the RST signal it returns to being high

sorry for my english... i understand??

you have some idea on like creating it?

1000 thanks...

Autor: Henrik (Gast)
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There are two ways to realize this:

1: You build a non-syncr. counter of this syncr. counters.
   Connect the RST output from the first counter with the
   CLK input of the second and so on.

2: Build a syncr. counter. (Better)
   Delete "and CLK='1'" in the if-Statement where RST is
generated.
   Connect the CE input from the second counter with RST
   from the first and connect ALL CLK's with each other.
   Example for the third counter: Create an AND with RST1 and RST2
   as inputs and connect CE of the third counter with this output.
   Example for the n-th counter: Create an AND with n-1 inputs and
   connect all RSTs from the counters before with them. The output
   of this AND shares the CE-Signal for the n-th Counter.

This should work (it's all UNTESTED).
(Well, this is hard work just for creating a simple
up/down-BCD-counter)

Greetings Henrik

P.S.: Or you use the super-function-wizard in your software creating a
BCD-counter! ;-)

Autor: italo (Gast)
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"P.S.: Or you use the super-function-wizard in your software creating
a
BCD-counter!"

what is this?? super-function-wizard? i use XILINX 6 where i can find
this???

Autor: italo (Gast)
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when i set half period clock in temp (CLK'event) te result is the
same...  it does not change nothing regarding before why?

thanks

Autor: Henrik (Gast)
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I don't know, how it is called in the Xillinx Software. I only knew the
one of Quartus, but I think Xillinx has such a "wizard" too.
This "wizard" is a code-generator, which constructs
standart-functions like counters, adders, multipliers etc for you. You
only have to import them into your project.

Greetings Henrik

Autor: italo (Gast)
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QUARTUS II? altera software? is this?

Autor: Henrik (Gast)
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Sorry, this with CLK'event was a mistake of me. Without "and
CLK='1'" the Signal RST must rise one half clock-cycle before. (And
get low one half clock-cycle before!)

Henrik

Autor: Henrik (Gast)
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Yes, Quartus 2 by Altera!

Henrik

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