Gast
#202212
when syntetize this code in VHDL I obtain this error "signal TEST cannot be syntetized" how can help me please??? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is port ( CLK: in STD_LOGIC; RESET: in STD_LOGIC; SET: in STD_LOGIC; RST: out STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; DIN: in STD_LOGIC_VECTOR(3 downto 0); TEST: inout STD_LOGIC_VECTOR(3 downto 0)); end counter; architecture Behavioral of counter is begin process(SET, RESET, LOAD, DIN, CE, DIR, TEST) begin if RESET='1' and DIR='1' then TEST <= "0000"; elsif LOAD='1' then TEST <= DIN; elsif SET='1' and SET'event then if CE='1' then if DIR='1' then if TEST="1001" then TEST <= "0000"; RST <='1'; else TEST <= TEST + "0001"; RST <='0'; end if; end if; end if; end if; if RESET='1' and DIR='0' then TEST <= "1001"; elsif LOAD='1' then TEST <= DIN; elsif SET='1' and SET'event then if CE='1' then if DIR='0' then if TEST="0000" then TEST <= "1001"; RST <='1'; else TEST <= TEST - "0001"; RST <='0'; end if; end if; end if; end if; end process; end Behavioral;