1 | #ifndef _OpencoreUart_HEADER_FILE_
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2 | #define _OpencoreUart_HEADER_FILE_
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3 |
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4 | #include <stddef.h>
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5 | #include "DDStructs.h"
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6 |
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7 | /***********************************************************************
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8 | * *
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9 | * UART PHYSICAL DEVICE SPECIFIC INFORMATION *
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10 | * *
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11 | ***********************************************************************/
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12 |
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13 | /* REGISTER OFFSETS FROM BASE ADDRESS */
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14 | #define OPENCOREUART_RXTX 0x00 //Receiver Buffer and Transmitter Holding Register (THR)
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15 | #define OPENCOREUART_IER 0x01 //Interrupt Enable Register
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16 | #define OPENCOREUART_IIR 0x02 //Interrupt Identification and FIFO Control Register
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17 | #define OPENCOREUART_LCR 0x03 //Line control Register
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18 | #define OPENCOREUART_MCR 0x04 //Modem control Register
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19 | #define OPENCOREUART_LSR 0x05 //Line status Register
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20 | #define OPENCOREUART_MSR 0x06 //Modem status Register
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21 |
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22 | /*
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23 | The registers can be accessed when the 7th (DLAB) bit of the Line Control Register is set to ‘1’. At
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24 | this time the above registers at addresses 0-1 can’t be accessed.
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25 | */
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26 | #define OPENCOREUART_DIVL 0x00 //Divisor Latch Byte 1 (LSB)
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27 | #define OPENCOREUART_DIVH 0x01 //Divisor Latch Byte 1 (MSB)
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28 |
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29 |
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30 |
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31 | #ifdef __cplusplus
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32 | extern "C"{
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33 | #endif /* __cplusplus */
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34 |
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35 | /* device initialization function */
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36 | void init_Opencoreuart( OpencoreuartCtx_t * ctx );
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37 |
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38 |
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39 | /*
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40 | * GPIO REGISTER MAPPING
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41 | */
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42 | typedef struct st_Opencoreuart_t{
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43 |
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44 | /* Receiver oder Transmit FIFO oder Divisor Latch Byte 1 (LSB) */ //REG-0//
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45 | volatile unsigned char rxtx;
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46 |
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47 | /* Interrupt Enable Register oder Divisor Latch Byte 1 (MSB) */ //REG-1//
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48 | volatile unsigned char ier;
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49 |
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50 | /* Interrupt Identification oder FIFO Control*/ //REG-2//
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51 | volatile unsigned char iir;
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52 |
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53 | /* Line Control Register */ //REG-3//
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54 | volatile unsigned char lcr;
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55 |
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56 | /* Modem Control Register */ //REG-4//
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57 | volatile unsigned char mcr;
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58 |
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59 | /* Line Status Register */ //REG-5//
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60 | volatile unsigned char lsr;
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61 |
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62 | /* Modem Status Register*/ //REG-6//
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63 | volatile unsigned char msr;
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64 |
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65 | }Opencoreuart_t;
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66 |
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67 |
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68 | /***********************************************************************
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69 | * *
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70 | * USER MACROS FOR READ/WRITE OPENCOREUART REGISTERS *
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71 | * *
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72 | ***********************************************************************/
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73 |
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74 | #define OPENCOREUART_WR_LCR(X,Y) ((volatile Opencoreuart_t *)((X)->base))->lcr=(Y)
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75 | //#define MICO_GPIO_WRITE_DATA(X,Y) ((volatile MicoGPIO_t *)((X)->base))->data=(Y)
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76 |
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77 |
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78 | #ifdef __cplusplus
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79 | }
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80 | #endif /* __cplusplus */
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81 | #endif//_OpencoreUart_HEADER_FILE_
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