ModelSim Fehler beim Volladdierer

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity FULL_ADD is

    Port ( A,B,CIN  : in   bit  ;

           SUM,COUT  : out  bit)  ;

end FULL_ADD;

architecture FA of FULL_ADD is

signal YINT1: bit_vector(2 downto 0);

signal YINT2: bit_vector(1 downto 0);

begin

  YINT1 <= (CIN,B,A);

  with YINT1 select

  YINT2  <=  "00" when "000",

        "01" when "001",

        "01" when "010",

        "10" when "011",

        "01" when "100",

        "10" when "101",

        "10" when "110",

        "11" when "111",

  SUM  <= YINT2(0);

  Cout  <= YINT2(1);

end FA;

vcom -work work -2002 -explicit {C:/Users/Nico/SkyDrive/Studium/3. Semester/Digitaltechnik/ISE_Projects/DIP1/Volladdierer.vhd}

Model Technology ModelSim PE Student Edition vcom 10.1c Compiler 2012.07 Jul 28 2012

-- Loading package STANDARD

-- Loading package TEXTIO

-- Loading package std_logic_1164

-- Loading package std_logic_arith

-- Loading package STD_LOGIC_UNSIGNED

-- Compiling entity FULL_ADD

-- Compiling architecture FA of FULL_ADD

** Error: C:/Users/Nico/SkyDrive/Studium/3. Semester/Digitaltechnik/ISE_Projects/DIP1/Volladdierer.vhd(46): Type error resolving infix expression "<=" as type std.STANDARD.BIT_VECTOR.

** Error: C:/Users/Nico/SkyDrive/Studium/3. Semester/Digitaltechnik/ISE_Projects/DIP1/Volladdierer.vhd(46): Cannot read output "SUM".

** Error: C:/Users/Nico/SkyDrive/Studium/3. Semester/Digitaltechnik/ISE_Projects/DIP1/Volladdierer.vhd(46): near ";": expecting WHEN or ','

** Error: C:/Users/Nico/SkyDrive/Studium/3. Semester/Digitaltechnik/ISE_Projects/DIP1/Volladdierer.vhd(49): VHDL Compiler exiting