Gast
#2920373
Hallo, Ich habe in VHDL ein JK-FF Programmiert und möchte es als Zähler nutzen. Schon wenn wenn es überhaupt nur genutzt wrden soll, Bekomme ich bei Implement Design die Fehlermeldung: WARNING:Par:100 - Design is not completely routed. There are 8 signals that are not completely routed in this design. See the "Z1.unroutes" file for a list of all unrouted signals. Check for other warnings in your PAR report that might indicate why these nets are unroutable. These nets can also be evaluated in FPGA Editor by selecting "Unrouted Nets" in the List Window. In Z1-Unrouted Steht nun: WARNING:ParHelpers:360 - Design is not completely routed. GLOBAL_LOGIC1 g0/Q g0/Q_not0001 led_0_OBUF led_0_OBUF1 led_1_OBUF led_2_OBUF led_3_OBUF Das Programm: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Z1 is Port (sw : in STD_LOGIC_VECTOR(7 downto 0); led : out STD_LOGIC_VECTOR(7 downto 0)); end Z1; architecture Behavioral of Z1 is component jkff --Die Komponente rsff soll genutzt werden port( Tackt : in STD_LOGIC; --Übergabe an die Komponente J : in STD_LOGIC; K : in STD_LOGIC; reset : in STD_LOGIC; Q : buffer STD_LOGIC); end Component; signal a: STD_LOGIC_Vector(3 downto 0); --Interne Signale begin g0: jkff port map (sw(0),sw(1),sw(2),sw(3),a(0)); led(0)<=sw(0); led(1)<=sw(1); led(2)<=sw(2); led(3)<=sw(3); led(4)<=a(0); end Behavioral; --JK-FF library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity JKFF is Port (Tackt,J,K,Reset: in STD_LOGIC; Q: buffer STD_LOGIC); end JKFF; architecture Behavioral of JKFF is begin process (Tackt,reset) begin if reset='1' then q<='0'; elsif (Tackt 'event and Tackt = '0') then if(J='1' and K = '0') then --Setzen q<='1'; elsif(j='0' and K = '1') then--Rüchsetzen q<='0'; elsif(j='1' and k='1') then--Toggeln q<=not q; else q<=q; end if; end if; end Process; end Behavioral; Wäre klasse wenn wenn jemand wüsste was nicht OK ist.