Hallo, ich habe LK Millers Tutorial 'blinkende LED' eingegeben und versucht zu kompilieren. Im Ergebnis gab es folgende Fehlermeldungen: " Waiting for 1 sub-compilation(s) to finish... FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files. Please recompile with -mt off -v 1 switch to identify which design unit failed. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files. Please recompile with -mt off -v 1 switch to identify which design unit failed. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Process "Simulate Behavioral Model" failed " Kann ir jemand erklären, was mir das sagen soll? Gruss Robert
R. Freitag schrieb: > FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 Welche Softwareversion? > Kann ir jemand erklären, was mir das sagen soll? Irgendwas mit deiner Installation ist faul oder am Projekt ist was arg verbastelt. Setz mal ein ganz neues Projekt auf und probiers nochmal...
R. Freitag schrieb: > FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the Google mit Fehlermeldung findet das: http://forums.xilinx.com/t5/General-Technical-Discussion/xilinx-14-2-bug-in-ubuntu/td-p/258516 MfG
R. Freitag schrieb: > FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the > generated C files. Erinnert mich auch an Abstürze mit modelsim. Dann passte entweder was mit den libraries oder den Port maps (componenten Instanziierung) nicht. Bei dir scheint auch der simulator das prob zu sein, nicht die Syndöse. Gruüß
Zu früh gefreut....:-(
beim kompilieren der gleichen Source tritt nach dem Installieren der
Treiber (von der vorhergehenden Meldung) folgendes auf:
Started : "Simulate Behavioral Model".
Determining files marked for global include in the design...
Running fuse...
Command Line: fuse -intstyle ise -incremental -o
/home/rfr/Dokumente/VHDL/LED/BlinkLED_tb_isim_beh.exe -prj
/home/rfr/Dokumente/VHDL/LED/BlinkLED_tb_beh.prj work.BlinkLED_tb {}
Running: /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle
ise -incremental -o
/home/rfr/Dokumente/VHDL/LED/BlinkLED_tb_isim_beh.exe -prj
/home/rfr/Dokumente/VHDL/LED/BlinkLED_tb_beh.prj work.BlinkLED_tb
ISim P.28xd (signature 0x54af6ca1)
Number of CPUs detected in this system: 2
Turning on mult-threading, number of parallel sub-compilation jobs: 4
Determining compilation order of HDL files
Parsing VHDL file "/home/rfr/Dokumente/VHDL/LED/BlinkLED.vhd" into
library work
Parsing VHDL file "/home/rfr/Dokumente/VHDL/LED/BlinkLED_tb.vhd" into
library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 37680 KB
Fuse CPU Usage: 2460 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling architecture behavioral of entity BlinkLED [blinkled_default]
Compiling architecture behavior of entity blinkled_tb
Time Resolution for simulation is 1ps.
FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the
generated C files. Please recompile with -mt off -v 1 switch to identify
which design unit failed. Process will terminate. For technical support
on this issue, please open a WebCase with this project attached at
http://www.xilinx.com/support.
FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the
generated C files. Please recompile with -mt off -v 1 switch to identify
which design unit failed. Process will terminate. For technical support
on this issue, please open a WebCase with this project attached at
http://www.xilinx.com/support.
Process "Simulate Behavioral Model" failed
Wie stelle ich das ab?
Gruss
Robert
R. Freitag schrieb: > beim kompilieren der gleichen Source Welcher Sorce denn? Kann ja sein, dass da ein Fehler drin ist, der den Compiler in die Ecke schickt...
Die hier... sollte bekannt vorkommen...:-) Gruss Robert
1 | ----------------------------------------------------------------------------------
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2 | -- Company:
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3 | -- Engineer:
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4 | --
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5 | -- Create Date: 16:49:44 12/18/2012
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6 | -- Design Name:
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7 | -- Module Name: BlinkLED - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description:
|
12 | --
|
13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 | library IEEE; |
21 | use IEEE.STD_LOGIC_1164.ALL; |
22 | |
23 | -- Uncomment the following library declaration if using
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24 | -- arithmetic functions with Signed or Unsigned values
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25 | --use IEEE.NUMERIC_STD.ALL;
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26 | |
27 | -- Uncomment the following library declaration if instantiating
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28 | -- any Xilinx primitives in this code.
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29 | --library UNISIM;
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30 | --use UNISIM.VComponents.all;
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31 | |
32 | library IEEE; |
33 | use IEEE.STD_LOGIC_1164.ALL; |
34 | use IEEE.NUMERIC_STD.ALL; |
35 | |
36 | entity BlinkLED is |
37 | Port ( clk : in STD_LOGIC; |
38 | led : out STD_LOGIC); |
39 | end BlinkLED; |
40 | |
41 | architecture Behavioral of BlinkLED is |
42 | |
43 | signal c : integer range 0 to 24999999 := 0; -- 0,5s bei 50MHz fosc |
44 | signal x : std_logic:= '0'; |
45 | |
46 | begin
|
47 | process begin |
48 | wait until rising_edge(clk); -- warten bis zum nächsten Takt |
49 | if (c<24999999) then -- 0…24999999 = 25000000 Takte = 1/2 Sekunde bei 50MHz |
50 | c <= c+1; -- wenn kleiner: weiterzählen |
51 | else -- wenn Zählerende erreicht: |
52 | c <= 0; -- Zähler zurücksetzen |
53 | x <= not x; -- und Signal x togglen |
54 | end if; |
55 | end process; |
56 | led <= x; -- Signal x an LED ausgeben |
57 | end Behavioral; |
R. Freitag schrieb: > Die hier... > sollte bekannt vorkommen...:-) > > Gruss Und wie schaut die TB (blinkled_tb) aus? Passen Component und Instanziierung zur entity? MfG
Hier die testbench. Die beiden Sources sind dem Tutorial von LK Miller entnommen und sollten eigentlich funktionieren.
1 | --------------------------------------------------------------------------------
|
2 | -- Company:
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3 | -- Engineer:
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4 | --
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5 | -- Create Date: 17:06:37 12/18/2012
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6 | -- Design Name:
|
7 | -- Module Name: /home/rfr/Dokumente/VHDL/LED/BlinkLED_tb.vhd
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8 | -- Project Name: LED
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9 | -- Target Device:
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10 | -- Tool versions:
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11 | -- Description:
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12 | --
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13 | -- VHDL Test Bench Created by ISE for module: BlinkLED
|
14 | --
|
15 | -- Dependencies:
|
16 | --
|
17 | -- Revision:
|
18 | -- Revision 0.01 - File Created
|
19 | -- Additional Comments:
|
20 | --
|
21 | -- Notes:
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22 | -- This testbench has been automatically generated using types std_logic and
|
23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
24 | -- that these types always be used for the top-level I/O of a design in order
|
25 | -- to guarantee that the testbench will bind correctly to the post-implementation
|
26 | -- simulation model.
|
27 | --------------------------------------------------------------------------------
|
28 | library IEEE; |
29 | use IEEE.STD_LOGIC_1164.ALL; |
30 | use IEEE.NUMERIC_STD.ALL; |
31 | |
32 | entity BlinkLED_tb is |
33 | -- leere Entity --> Testbench
|
34 | end BlinkLED_tb; |
35 | |
36 | architecture behavior of BlinkLED_tb is |
37 | component BlinkLED |
38 | port( clk : IN std_logic; |
39 | led : OUT std_logic ); |
40 | end component; |
41 | |
42 | signal clk : std_logic := '0'; -- lokale Signale der Testbench |
43 | signal led : std_logic; -- werden an den Prüfling angeschlossen |
44 | |
45 | begin
|
46 | uut: BlinkLED -- der Prüfling wird verdrahtet |
47 | port map ( clk => clk, |
48 | led => led ); |
49 | |
50 | clk <= not clk after 10 ns; -- einen 50MHz Takt erzeugen |
51 | end; |
R. Freitag schrieb: > sollte bekannt vorkommen...:-) Ja, das sollte auch funktionieren... Was passiert, wenn du mal absichtlich das falsche Modul (die BlinkLED) als Toplevel zur Simulation gibst?
das hier:
Started : "Simulate Behavioral Model".
Determining files marked for global include in the design...
Running fuse...
Command Line: fuse -intstyle ise -incremental -o
/home/rfr/Dokumente/VHDL/LED/BlinkLED_isim_beh.exe -prj
/home/rfr/Dokumente/VHDL/LED/BlinkLED_beh.prj work.BlinkLED {}
Running: /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle
ise -incremental -o /home/rfr/Dokumente/VHDL/LED/BlinkLED_isim_beh.exe
-prj /home/rfr/Dokumente/VHDL/LED/BlinkLED_beh.prj work.BlinkLED
ISim P.28xd (signature 0x54af6ca1)
Number of CPUs detected in this system: 2
Turning on mult-threading, number of parallel sub-compilation jobs: 4
Determining compilation order of HDL files
Parsing VHDL file "/home/rfr/Dokumente/VHDL/LED/BlinkLED.vhd" into
library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 37676 KB
Fuse CPU Usage: 2390 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling architecture behavioral of entity blinkled
Time Resolution for simulation is 1ps.
FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the
generated C files. Please recompile with -mt off -v 1 switch to identify
which design unit failed. Process will terminate. For technical support
on this issue, please open a WebCase with this project attached at
http://www.xilinx.com/support.
FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the
generated C files. Please recompile with -mt off -v 1 switch to identify
which design unit failed. Process will terminate. For technical support
on this issue, please open a WebCase with this project attached at
http://www.xilinx.com/support.
Process "Simulate Behavioral Model" failed
Also mit 14.3 hier unter Win7 x64 gibts mit den beiden Dateien keine Probleme.
Mein Problem besteht darin, dass ich nicht weiss, was mir diese Fehlermeldungen eingentlich sagen wollen. Ich kann nicht aus diesen Meldungen auf die Ursache schliessen. Robert
Scheint ein Problem mit dem Simlator zu sein. Optimierung für den Simulator abschalten, bspw. multithread. Andere .vhd files versuchen, ältere/neuere ISE benutzen. Cleanup-Projekt-files hast du schon versucht?
Angehängte Dateien:
-
blink_simulation.png
48 KB
R. Freitag schrieb: > Hier die testbench. Die beiden Sources sind dem Tutorial von LK Miller > entnommen und sollten eigentlich funktionieren. Die funktionieren auch. Siehe Anhang. Ich würde eine Neuinstallation der Xilinx-Tools vorschlagen. Duke
R. Freitag schrieb: > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity BlinkLED is > Port ( clk : in STD_LOGIC; > led : out STD_LOGIC); > end BlinkLED; vlt. einen Versuch wert: Loesch mal die doppelten Libs raus.
Ich habe die gleiche Version installiert, weil ich in der vorhergehenden Install die Zugriffe auf den USBBus nicht vollständig erhalten habe. Dieser Fehler ist nun verschwunden. Der erwähnte Fehler ist neu, aber er trat auch vorher schon auf. Robert
Angehängte Dateien:
Auch im ISim 13.3 funktioniert es:
1 | Running: fuse.exe -relaunch -intstyle "ise" -incremental -o "C:/blinky/BlinkLED_tb_isim_beh.exe" -prj "C:/blinky/BlinkLED_tb_beh.prj" "work.BlinkLED_tb" |
2 | ISim O.76xd (signature 0x2f00eba5) |
3 | Number of CPUs detected in this system: 6 |
4 | Turning on mult-threading, number of parallel sub-compilation jobs: 12 |
5 | Determining compilation order of HDL files |
6 | Parsing VHDL file "C:/blinky/blink.vhd" into library work |
7 | Parsing VHDL file "C:/blinky/blink_tb.vhd" into library work |
8 | Starting static elaboration |
9 | Completed static elaboration |
10 | Fuse Memory Usage: 121316 KB |
11 | Fuse CPU Usage: 296 ms |
12 | Compiling package standard |
13 | Compiling package std_logic_1164 |
14 | Compiling package numeric_std |
15 | Compiling architecture behavioral of entity BlinkLED [blinkled_default] |
16 | Compiling architecture behavior of entity blinkled_tb |
17 | Time Resolution for simulation is 1ps. |
18 | Waiting for 1 sub-compilation(s) to finish... |
19 | Compiled 6 VHDL Units |
20 | Built simulation executable C:/blinky/BlinkLED_tb_isim_beh.exe |
21 | Fuse Memory Usage: 136852 KB |
22 | Fuse CPU Usage: 483 ms |
23 | ========== Fuse: succeeded ========== |
Duke
berndl schrieb: > R. Freitag schrieb: >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> use IEEE.NUMERIC_STD.ALL; >> >> entity BlinkLED is >> Port ( clk : in STD_LOGIC; >> led : out STD_LOGIC); >> end BlinkLED; > > vlt. einen Versuch wert: Loesch mal die doppelten Libs raus. erledigt---keine Änderung. Robert
R. Freitag schrieb: > /home/rfr/Dokumente/VHDL/LED/BlinkLED_isim_beh.exe -prj > /home/rfr/Dokumente/VHDL/LED/BlinkLED_beh.prj work.BlinkLED {} Hm, du verwendest Linux? ISE hat probleme beim compilieren von C-Code? Vielleicht tut es ja mit ISE mit priviliegierten Rechten? MfG
Felix Finder schrieb: > R. Freitag schrieb: >> /home/rfr/Dokumente/VHDL/LED/BlinkLED_isim_beh.exe -prj >> /home/rfr/Dokumente/VHDL/LED/BlinkLED_beh.prj work.BlinkLED {} > > > Hm, du verwendest Linux? ISE hat probleme beim compilieren von C-Code? > Vielleicht tut es ja mit ISE mit priviliegierten Rechten? > > MfG Oder muss man des devel paket installieren? Xilinx gibt die ISE meist nur für eine Linux Distri frei.
Ich habe jetzt die 14.4.40 installiert, der gleiche Fehler tritt immer noch auf. Was kann man noch tun?? Grüsse Robert
R. Freitag schrieb: > Please recompile with -mt off -v 1 switch to identify > which design unit failed. Hast du das mal probiert? Im Zweifelsfall hast du einen Bug in der Linux Variante gefunden.
In ISE bei Simulation kannst du rechte Maustaste auf Simulate Behavioral Model -> Process Properties und dann die switches bei "Other compiler options" rein schreiben.
Christian R. schrieb: > In ISE bei Simulation kannst du rechte Maustaste auf Simulate Behavioral > Model -> Process Properties und dann die switches bei "Other compiler > options" rein schreiben. Result: Started : "Simulate Behavioral Model". Determining files marked for global include in the design... Running fuse... Command Line: fuse -intstyle ise -incremental -o /home/rfr/Dokumente/VHDL/LED/BlinkLED_isim_beh.exe -prj /home/rfr/Dokumente/VHDL/LED/BlinkLED_beh.prj work.BlinkLED {-mt off -v 1} Running: /opt/Xilinx/14.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/rfr/Dokumente/VHDL/LED/BlinkLED_isim_beh.exe -prj /home/rfr/Dokumente/VHDL/LED/BlinkLED_beh.prj work.BlinkLED -mt off -v 1 ISim P.49d (signature 0xfbc00daa) Turned off multi-threading for compilation Determining compilation order of HDL files The vhdl library search path for library \"std\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/std\" The veri library search path for library \"std\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/std\" The vhdl library search path for library \"ieee\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/ieee\" The veri library search path for library \"ieee\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/ieee\" The vhdl library search path for library \"ieee_proposed\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/ieee_proposed\" The veri library search path for library \"ieee_proposed\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/ieee_proposed\" The vhdl library search path for library \"vl\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/vl\" The veri library search path for library \"vl\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/vl\" The vhdl library search path for library \"synopsys\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/synopsys\" The veri library search path for library \"synopsys\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/synopsys\" The vhdl library search path for library \"simprim\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/simprim\" The veri library search path for library \"simprim\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/simprim\" The vhdl library search path for library \"unisim\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/unisim\" The veri library search path for library \"unisim\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/unisim\" The vhdl library search path for library \"unimacro\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/unimacro\" The veri library search path for library \"unimacro\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/unimacro\" The vhdl library search path for library \"aim\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/aim\" The veri library search path for library \"aim\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/aim\" The vhdl library search path for library \"cpld\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/cpld\" The veri library search path for library \"cpld\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/cpld\" The vhdl library search path for library \"pls\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/pls\" The veri library search path for library \"pls\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/pls\" The vhdl library search path for library \"xilinxcorelib\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/xilinxcorelib\" The veri library search path for library \"xilinxcorelib\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/vhdl/hdp/lin/xilinxcorelib\" The vhdl library search path for library \"aim_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/aim_ver\" The veri library search path for library \"aim_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/aim_ver\" The vhdl library search path for library \"cpld_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/cpld_ver\" The veri library search path for library \"cpld_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/cpld_ver\" The vhdl library search path for library \"simprims_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/simprims_ver\" The veri library search path for library \"simprims_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/simprims_ver\" The vhdl library search path for library \"unisims_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/unisims_ver\" The veri library search path for library \"unisims_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/unisims_ver\" The vhdl library search path for library \"uni9000_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/uni9000_ver\" The veri library search path for library \"uni9000_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/uni9000_ver\" The vhdl library search path for library \"unimacro_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/unimacro_ver\" The veri library search path for library \"unimacro_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/unimacro_ver\" The vhdl library search path for library \"xilinxcorelib_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/xilinxcorelib_ver\" The veri library search path for library \"xilinxcorelib_ver\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/xilinxcorelib_ver\" The vhdl library search path for library \"secureip\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/xip/secureip\" The veri library search path for library \"secureip\" is now \"/opt/Xilinx/14.4/ISE_DS/ISE/verilog/hdp/lin/xip/secureip\" The vhdl library search path for library \"work\" is now \"/home/rfr/Dokumente/VHDL/LED/isim/work\" The veri library search path for library \"work\" is now \"/home/rfr/Dokumente/VHDL/LED/isim/work\" -- Dumping Relevant Parameters XILINX = /opt/Xilinx/14.4/ISE_DS/ISE/ PATH = /opt/Xilinx/14.4/ISE_DS/ISE//bin/lin:/home/rfr/bin:/usr/local/bin:/usr/b in:/bin:/usr/bin/X11:/usr/X11R6/bin:/usr/games:/opt/kde3/bin:/opt/cross/ bin LD_LIBRARY_PATH = /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin PWD = /home/rfr CWD = /home/rfr/Dokumente/VHDL/LED GCC = /usr/bin/gcc -- Done dumping Relevant Parameters -- Dumping System Information sysname = Linux release = 3.4.11-2.16-desktop version = #1 SMP PREEMPT Wed Sep 26 17:05:00 UTC 2012 (259fc87) machine = i686 ram = 4085488 KB -- Done dumping System Information -- Dumping Loaded Modules /lib/ld-linux.so.2 /lib/libc.so.6 /lib/libdl.so.2 /lib/libgcc_s.so.1 /lib/libm.so.6 /lib/libpthread.so.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libCit_Core.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libICR.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libMiniZip.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libPersonalityModule.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libPort_Std.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libPortability.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libPrjrep_Clientac.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libStaticFileParsers.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libThread.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libUtilities.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libVrfc_Verific.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libVrfc_Vhdl_Sort.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libZlib.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libboost_bzip2-gcc41-mt-p-1_38.so.1 .38.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libboost_date_time-gcc41-mt-p-1_38. so.1.38.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libboost_filesystem-gcc41-mt-p-1_38 .so.1.38.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libboost_iostreams-gcc41-mt-p-1_38. so.1.38.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libboost_program_options-gcc41-mt-p -1_38.so.1.38.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libboost_regex-gcc41-mt-p-1_38.so.1 .38.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libboost_system-gcc41-mt-p-1_38.so. 1.38.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libboost_thread-gcc41-mt-p-1_38.so. 1.38.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libboost_zlib-gcc41-mt-p-1_38.so.1. 38.0 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libisl_iostreams.so /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstlport.so.5.1 /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libxercesc.so /opt/Xilinx/14.4/ISE_DS/ISE/lib/lin/libUtilC_MessageDispatcher.so /usr/lib/libuuid.so.1 linux-gate.so.1 -- Done dumping Loaded Modules -- Dumping library mapping aim=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/aim aim_ver=/opt/Xilinx/14.4/ISE_DS/ISE/./verilog/hdp/lin/aim_ver cpld=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/cpld cpld_ver=/opt/Xilinx/14.4/ISE_DS/ISE/./verilog/hdp/lin/cpld_ver ieee=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/ieee ieee_proposed=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/ieee_proposed pls=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/pls secureip=/opt/Xilinx/14.4/ISE_DS/ISE/./verilog/hdp/lin/xip/secureip simprim=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/simprim simprims_ver=/opt/Xilinx/14.4/ISE_DS/ISE/./verilog/hdp/lin/simprims_ver std=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/std synopsys=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/synopsys uni9000_ver=/opt/Xilinx/14.4/ISE_DS/ISE/./verilog/hdp/lin/uni9000_ver unimacro=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/unimacro unimacro_ver=/opt/Xilinx/14.4/ISE_DS/ISE/./verilog/hdp/lin/unimacro_ver unisim=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/unisim unisims_ver=/opt/Xilinx/14.4/ISE_DS/ISE/./verilog/hdp/lin/unisims_ver vl=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/vl work=isim/work xilinxcorelib=/opt/Xilinx/14.4/ISE_DS/ISE/./vhdl/hdp/lin/xilinxcorelib xilinxcorelib_ver=/opt/Xilinx/14.4/ISE_DS/ISE/./verilog/hdp/lin/xilinxco relib_ver -- Done dumping library mapping Parsing VHDL file "/home/rfr/Dokumente/VHDL/LED/BlinkLED.vhd" into library work Parsing entity <BlinkLED>. Parsing architecture <Behavioral> of entity <blinkled>. Starting static elaboration WARNING:HDLCompiler:746 - "/build/xfndry10/P.49d/rtf/vhdl/src/ieee/numeric_std.vhd" Line 878: Range is empty (null range) WARNING:HDLCompiler:746 - "/build/xfndry10/P.49d/rtf/vhdl/src/ieee/numeric_std.vhd" Line 879: Range is empty (null range) Executing BlinkLED(Behavioral) Completed static elaboration Fuse Memory Usage: 37684 KB Fuse CPU Usage: 2480 ms Compiling package standard - standard ICR Memory Use: 4294967295 bytes Compiling package std_logic_1164 - p_2592010699 (incremental note: generated C did not change and C compilation will be skipped) ICR Memory Use: 622639 bytes Compiling package numeric_std - p_1242562249 (incremental note: generated C did not change and C compilation will be skipped) ICR Memory Use: 449392 bytes Compiling architecture behavioral of entity blinkled - a_4219172281_3212880686 ICR Memory Use: 9963 bytes Compiling isim/BlinkLED_isim_beh.exe.sim/work/a_4219172281_3212880686.c to isim/BlinkLED_isim_beh.exe.sim/work/a_4219172281_3212880686.lin.o with command: "/usr/bin/gcc" -Wa,-W -O -m32 -c -o "isim/BlinkLED_isim_beh.exe.sim/work/a_4219172281_3212880686.lin.o" -I"/opt/Xilinx/14.4/ISE_DS/ISE/./data/include" "isim/BlinkLED_isim_beh.exe.sim/work/a_4219172281_3212880686.c" /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libppl_c.so.4) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/libppl_c.so.4) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.15' not found (required by /usr/lib/libppl_c.so.4) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libppl.so.9) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/libppl.so.9) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.15' not found (required by /usr/lib/libppl.so.9) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libgmpxx.so.4) FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/BlinkLED_isim_beh.exe.sim/work/a_4219172281_3212880686.c Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/BlinkLED_isim_beh.exe.sim/work/a_4219172281_3212880686.c Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Process "Simulate Behavioral Model" failed
Nach einigen Änderungen ergibt sich eine neue Fehlermeldung: Compiling isim/precompiled.exe.sim/ieee/p_2592010699.c to isim/precompiled.exe.sim/ieee/p_2592010699.lin.o with command: "/usr/bin/gcc" -Wa,-W -O -m32 -c -o "isim/precompiled.exe.sim/ieee/p_2592010699.lin.o" -I"/opt/Xilinx/14.4/ISE_DS/ISE/./data/include" "isim/precompiled.exe.sim/ieee/p_2592010699.c" /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libppl_c.so.4) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/libppl_c.so.4) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.15' not found (required by /usr/lib/libppl_c.so.4) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libppl.so.9) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/libppl.so.9) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.15' not found (required by /usr/lib/libppl.so.9) /usr/lib/gcc/i586-suse-linux/4.7/cc1: /opt/Xilinx/14.4/ISE_DS/ISE//lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libgmpxx.so.4) FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/precompiled.exe.sim/ieee/p_2592010699.c Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/precompiled.exe.sim/ieee/p_2592010699.c Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Process "Simulate Behavioral Model" failed Was tun? Gruss Robert
Das scheint ein Linux Problem mit der GLIBC zu sein, da kenn ich mich nicht aus. Unter Windows hat man schon genug Probleme mit ISE, da will ich mir das Gefrickel unter Linux erst recht nicht antun.
Hi, Den Fehler kenn ich. Deine Linux Distribution verwendet eine andere libc-Version als in ISE enthalten ist. Die Xilinx Version ist recht alt wegen den Enterprise-Distibutionen. Lösung gib's zb bei Wiki.ubuntuusers.de bzw. bei Wiki.archlinux.org http://wiki.ubuntuusers.de/Xilinx_ISE Gruß
Xilinx scheint überhaupt eine veraltete Version von GCC zu verwenden, um ihre Compilationen zu erstellen. Mit hat kürzlich mal ein Linuxfachmann vorgerechnet, was die alles an Unfug treiben. Ich kann es gar nicht alles wiedergeben.
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