FIR-Filter mit Eingangsrate > Ausgangsrate

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity filter2 is

    port(

        CLK : in  std_logic;                    --Clock

        X   : in  std_logic_vector(8 downto 0); --9Bit input

        Y   : out std_logic_vector(14 downto 0) --15bit output

    );

end filter2;

architecture Behavioral of filter2 is

    signal y_0 : std_logic_vector(14 downto 0);

    signal y_1 : std_logic_vector(14 downto 0);

    signal x_1 : std_logic_vector(8 downto 0);

    signal x_2 : std_logic_vector(8 downto 0);

    signal x_3 : std_logic_vector(8 downto 0);

    signal x_4 : std_logic_vector(8 downto 0);

    signal xsum  : std_logic_vector(8 downto 0);

    signal xsumq : std_logic_vector(14 downto 0);

    signal cnt : std_logic_vector(1 downto 0);

begin

    --Sum of x(n), x(n-4) ;  8bit addition

    xsum <= std_logic_vector(signed(X)-signed(x_4));

    --Quarter of xsum & 8bit -> 15bit

    --       positiv                                             negative

    xsumq <= "00000000" & xsum(8 downto 2) when xsum(8)='0' else "11111111" & xsum(8 downto 2);

    --Registers

    Registers : process(CLK, X, y_0)

    begin

        if rising_edge(CLK) then

            y_1 <= y_0;

            x_1 <= X;

            x_2 <= x_1;

            x_3 <= x_2;

            x_4 <= x_3;

            --Output register ;   15bit addition

            if cnt="11" then

                y_0 <= std_logic_vector(signed(xsumq)+signed(y_1));

            else

                y_0 <= y_0;

            end if;--cnt

        end if;--CLK

    end process Registers;

    --Counter

    Counter : process(CLK)

    begin

        if rising_edge(CLK) then

            cnt <= std_logic_vector(unsigned(cnt)+1);

        end if;--CLK

    end process Counter;

    --Y output

    Y <= y_0;

end Behavioral;