Lattice MachXo2 iCE40 Config Loader

Link:
Beitrag "SPI Master Configuration Interface für iCE 40 (Lattice)"

Bild: Flow Chart iC40_MOD_2.PNG
Project: Lattice MachXo2 iCE40 Config Loader.
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Via ispVM Tool: Im "SPI-MODE" u. via *.bin File
wird ein iCE40 Prom-Design-Image ab    Start-Adress: 0x0-0000
......bin-File
in das externe Flash-SPI-Rom geladen. (Stop-Adresse: 0x1-0000)
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Bin-File via JTAG--> MachXo2 --<<|>ext.{SPI-PROM M25P10}
---<> IceBlink ice40-HX1K Evaluation Board.
http://www.latticesemi.com/support/faqs/details.cfm?id=1702
Which pin should be used for the EFB SPI clock in a MachXO2
design using the hardened SPI ...

Answer:
-------------------------------------
The MachXO2 has "2" hardened SPI cores
tied to the internal FPGA configuration logic.
These cores can be accessed through an internal bus interface (wishbone)
by instantiating the Embedded Function Block (EFB) element in HDL code.
The SPI cores have a "hardened architecture" inside the EFB
and specific external configuration pins are required to be tied to the 
SPI cores.
The spi_clk pin for the hardened SPI IP core is routed to CCLK/MCLK pin,
which is the dedicated configuration clock port for the SPI programming 
port.

Further information on the SPI ports
can be located in TN1205, in the "Hardened SPI IP Core" section.
http://www.latticesemi.com/documents/TN1205.pdf
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Link-2:

http://www.latticesemi.com/documents/TN1204.pdf
Gruss Holger.