1 | // ERSTER INTERRUPT INITITALISIEREN
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2 | /* Recast the edge_capture pointer to match the alt_irq_register() function prototype. */
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3 | // siehe http://www.mikrocontroller.net/topic/229699
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4 | void* edge_capture_ptr = (void*) &edge_capture;
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5 | /* Enable first 31 interrupts. */
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6 | IOWR_ALTERA_AVALON_PIO_IRQ_MASK(INPUT_0_IRQ_BASE, 0xFFFFFFFF);
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7 | /* Reset the edge capture register. */
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8 | IOWR_ALTERA_AVALON_PIO_EDGE_CAP(INPUT_0_IRQ_BASE, 0x00000000);
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9 | /* Register the interrupt handler. */
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10 | alt_irq_register(INPUT_0_IRQ_IRQ, edge_capture_ptr, handle_pio_interrupts);
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11 |
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12 | // ZWEITER INTERRUPT INITITALISIEREN
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13 | /* Recast the edge_capture pointer to match the alt_irq_register() function prototype. */
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14 | // siehe http://www.mikrocontroller.net/topic/229699
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15 | void* edge_capture2_ptr = (void*) &edge_capture2;
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16 | /* Enable first 31 interrupts. */
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17 | IOWR_ALTERA_AVALON_PIO_IRQ_MASK(INPUT_2_IRQ_BASE, 0xFFFFFFFF);
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18 | /* Reset the edge capture register. */
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19 | IOWR_ALTERA_AVALON_PIO_EDGE_CAP(INPUT_2_IRQ_BASE, 0x00000000);
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20 | /* Register the interrupt handler. */
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21 | alt_irq_register(INPUT_2_IRQ_IRQ, edge_capture2_ptr, handle_pio2_interrupts);
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22 |
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23 | .
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24 | .
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25 | .
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26 |
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27 | // SECHSTER INTERRUPT INITITALISIEREN
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28 | /* Recast the edge_capture pointer to match the alt_irq_register() function prototype. */
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29 | // siehe http://www.mikrocontroller.net/topic/229699
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30 | void* edge_capture6_ptr = (void*) &edge_capture6;
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31 | /* Enable first 31 interrupts. */
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32 | IOWR_ALTERA_AVALON_PIO_IRQ_MASK(INPUT_6_IRQ_BASE, 0xFFFFFFFF);
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33 | /* Reset the edge capture register. */
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34 | IOWR_ALTERA_AVALON_PIO_EDGE_CAP(INPUT_6_IRQ_BASE, 0x00000000);
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35 | /* Register the interrupt handler. */
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36 | alt_irq_register(INPUT_6_IRQ_IRQ, edge_capture6_ptr, handle_pio6_interrupts);
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37 |
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38 |
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39 | void handle_pio_interrupts(void* context, alt_u32 id)
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40 | {
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41 | /* Cast context to edge_capture's type. It is important that this be
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42 | * declared volatile to avoid unwanted compiler optimization. */
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43 | volatile int* edge_capture_ptr = (volatile int*) context;
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44 |
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45 | /* Store the value in the PIO's edge capture register in *context. */
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46 | *edge_capture_ptr = IORD_ALTERA_AVALON_PIO_EDGE_CAP(INPUT_0_IRQ_BASE);
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47 |
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48 | //Wenn ein IR auftritt, dann in Buffer speichern
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49 | SendeDaten = IORD_ALTERA_AVALON_PIO_DATA(INPUT_0_IRQ_BASE);
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50 | BufferIn(SendeDaten);
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51 |
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52 | /* Reset the PIO's edge capture register. */
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53 | IOWR_ALTERA_AVALON_PIO_EDGE_CAP(INPUT_0_IRQ_BASE, 0);
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54 |
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55 |
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56 | }
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57 |
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58 |
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59 | void handle_pio2_interrupts(void* context, alt_u32 id)
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60 | {
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61 | /* Cast context to edge_capture's type. It is important that this be
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62 | * declared volatile to avoid unwanted compiler optimization. */
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63 | volatile int* edge_capture2_ptr = (volatile int*) context;
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64 |
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65 | /* Store the value in the PIO's edge capture register in *context. */
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66 | *edge_capture2_ptr = IORD_ALTERA_AVALON_PIO_EDGE_CAP(INPUT_2_IRQ_BASE);
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67 |
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68 | //Wenn ein IR auftritt, dann in Buffer speichern
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69 | SendeDaten = IORD_ALTERA_AVALON_PIO_DATA(INPUT_2_IRQ_BASE);
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70 | BufferIn(SendeDaten);
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71 |
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72 | /* Reset the PIO's edge capture register. */
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73 | IOWR_ALTERA_AVALON_PIO_EDGE_CAP(INPUT_2_IRQ_BASE, 0);
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74 |
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75 |
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76 | }
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77 | .
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78 | .
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79 | .
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80 | void handle_pio6_interrupts(void* context, alt_u32 id)
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81 | {
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82 | /* Cast context to edge_capture's type. It is important that this be
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83 | * declared volatile to avoid unwanted compiler optimization. */
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84 | volatile int* edge_capture6_ptr = (volatile int*) context;
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85 |
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86 | /* Store the value in the PIO's edge capture register in *context. */
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87 | *edge_capture6_ptr = IORD_ALTERA_AVALON_PIO_EDGE_CAP(INPUT_6_IRQ_BASE);
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88 |
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89 | //Lese aus Buffer (aus der letzten belegten Stelle)
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90 | check = BufferOut(EmpfangsDaten);
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91 | if(check == 0){
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92 | IOWR_ALTERA_AVALON_PIO_DATA(OUTPUT_0_BASE, 0xCAFEAFFE);
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93 | }
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94 | else{
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95 | IOWR_ALTERA_AVALON_PIO_DATA(OUTPUT_0_BASE, *EmpfangsDaten);
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96 | }
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97 | /* Reset the PIO's edge capture register. */
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98 | IOWR_ALTERA_AVALON_PIO_EDGE_CAP(INPUT_6_IRQ_BASE, 0);
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99 |
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100 |
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101 | }
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