Hallo,
ich bin noch relativ neu im Thema VHDL und stehe nun vor einem Problem:
Bei der Simulation eines eigentlich einfachen Zählers taucht eine für
mich nicht verständliche Warnung im ModelSim auf:
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 100 ns Iteration: 1 Instance: /testbench_zaehler/t1
Folgender Code liegt vor:
>Zaehler
1 | LIBRARY IEEE ;
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2 | USE IEEE.STD_LOGIC_1164.ALL;
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3 | USE IEEE.STD_LOGIC_ARITH.ALL ;
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4 | USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
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5 |
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6 | ENTITY zaehler IS
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7 | PORT (clk, en : IN STD_LOGIC ;
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8 | q : OUT STD_LOGIC_VECTOR (3 downto 0));
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9 | END zaehler;
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10 |
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11 | ARCHITECTURE behav OF zaehler IS
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12 |
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13 | SIGNAL q_s : STD_LOGIC_VECTOR (3 DOWNTO 0);
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14 |
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15 | BEGIN
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16 |
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17 | p1 : PROCESS (clk)
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18 |
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19 | BEGIN
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20 |
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21 | IF ( clk'EVENT AND clk = '1' AND clk'LAST_VALUE = '0') THEN
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22 | IF (en = '1') THEN q_s <= q_s + "0001"; END IF;
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23 | IF (en = '1' AND q_s = "1001") THEN q_s <="0000"; END IF ;
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24 | END IF ;
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25 |
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26 | END PROCESS p1 ;
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27 |
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28 | q <= q_s;
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29 |
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30 | END behav ;
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>Stimulus
1 | LIBRARY IEEE;
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2 | USE IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | ENTITY stimulus_zaehler IS
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5 | PORT( clk, en : OUT STD_LOGIC );
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6 | END stimulus_zaehler ;
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7 |
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8 | ARCHITECTURE behav OF stimulus_zaehler IS
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9 | SIGNAL clk_s: STD_LOGIC:='0';
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10 | BEGIN
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11 | clk_s <= NOT clk_s AFTER 100 ns;
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12 | clk <= clk_s ;
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13 | en <= '0', '1' AFTER 80 ns, '0' AFTER 3000 ns, '1' AFTER 3500 ns;
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14 |
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15 | END behav ;
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>Testbench
1 | LIBRARY IEEE;
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2 | USE IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | ENTITY testbench_zaehler IS
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5 | PORT(q_g: OUT STD_LOGIC_VECTOR (3 downto 0));
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6 | END testbench_zaehler;
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7 |
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8 | ARCHITECTURE behav_testbench_zaehler OF testbench_zaehler IS
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9 |
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10 | SIGNAL en_g, clk_g: STD_LOGIC;
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11 |
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12 | COMPONENT zaehler
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13 | PORT (clk, en : IN STD_LOGIC ;
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14 | q : OUT STD_LOGIC_VECTOR (3 downto 0));
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15 | END COMPONENT;
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16 |
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17 | COMPONENT stimulus_zaehler
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18 | PORT (clk, en : OUT STD_LOGIC );
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19 | END COMPONENT;
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20 |
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21 | BEGIN
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22 | t1: zaehler PORT MAP (clk=>clk_g, en=>en_g, q=>q_g);
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23 | t2: stimulus_zaehler PORT MAP (clk=>clk_g, en=>en_g);
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24 | END behav_testbench_zaehler;
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Für Hinweise wo der Fehler zu finden ist bin ich sehr dankbar!
Vielen Dank!
LG K.
