Hallo Zusammen
Wenn ich mit Mentor Graphics meine VHDL Files generieren lasse kommt
folgendes raus
1 | -- VHDL Entity FPGA_Box.Puls_Generator.symbol
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2 | --
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3 | -- Created:
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4 | -- by - chrebhu.UNKNOWN (CHSEM00-6-103)
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5 | -- at - 13:41:22 04.02.2014
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6 | --
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7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2010.3 (Build 21)
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8 | --
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9 | LIBRARY ieee;
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10 | USE ieee.std_logic_1164.all;
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11 | USE ieee.std_logic_arith.all;
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12 |
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13 | ENTITY Puls_Generator IS
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14 | PORT(
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15 | SM_control : IN std_logic_vector (7 DOWNTO 0);
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16 | SM_mode : IN std_logic_vector (7 DOWNTO 0);
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17 | Uzw_thres : IN std_logic;
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18 | clk : IN std_logic;
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19 | npuls : IN unsigned (7 DOWNTO 0);
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20 | rst : IN std_logic;
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21 | tmag_off : IN natural RANGE 31 DOWNTO 0;
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22 | tmag_on : IN natural RANGE 31 DOWNTO 0;
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23 | toff : IN natural RANGE 31 DOWNTO 0;
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24 | ton : IN natural RANGE 31 DOWNTO 0;
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25 | tvor : IN natural RANGE 31 DOWNTO 0;
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26 | umon_trig : IN unsigned (15 DOWNTO 0);
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27 | SM_status : OUT std_logic_vector (7 DOWNTO 0);
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28 | cs_DUT : OUT std_logic;
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29 | cs_vor : OUT std_logic;
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30 | trig_monitor : OUT std_logic
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31 | );
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32 |
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33 | -- Declarations
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34 |
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35 | END Puls_Generator ;
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36 |
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37 | --
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38 | -- VHDL Architecture FPGA_Box.Puls_Generator.fsm
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39 | --
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40 | -- Created:
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41 | -- by - chrebhu.UNKNOWN (CHSEM00-6-103)
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42 | -- at - 13:41:23 04.02.2014
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43 | --
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44 | -- Generated by Mentor Graphics' HDL Designer(TM) 2010.3 (Build 21)
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45 | --
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46 | LIBRARY ieee;
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47 | USE ieee.std_logic_1164.all;
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48 | USE ieee.std_logic_arith.all;
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49 |
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50 | ARCHITECTURE fsm OF Puls_Generator IS
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Dabei ist zu sehen, dass sowohle vor der Entity als auch vor der
Architektur Library Deklarationen aufgeführt sind.
Ich frage mich nun, weshalb das so ist, bzw. was der Sinn und Zweck der
zweimaligen Library Deklarationen ist.
Gruss