Library Deklaration bevor ENTITY oder bevor ARCHITECURE

-- VHDL Entity FPGA_Box.Puls_Generator.symbol

--

-- Created:

--          by - chrebhu.UNKNOWN (CHSEM00-6-103)

--          at - 13:41:22 04.02.2014

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2010.3 (Build 21)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY Puls_Generator IS

   PORT( 

      SM_control   : IN     std_logic_vector (7 DOWNTO 0);

      SM_mode      : IN     std_logic_vector (7 DOWNTO 0);

      Uzw_thres    : IN     std_logic;

      clk          : IN     std_logic;

      npuls        : IN     unsigned (7 DOWNTO 0);

      rst          : IN     std_logic;

      tmag_off     : IN     natural RANGE 31 DOWNTO 0;

      tmag_on      : IN     natural RANGE 31 DOWNTO 0;

      toff         : IN     natural RANGE 31 DOWNTO 0;

      ton          : IN     natural RANGE 31 DOWNTO 0;

      tvor         : IN     natural RANGE 31 DOWNTO 0;

      umon_trig    : IN     unsigned (15 DOWNTO 0);

      SM_status    : OUT    std_logic_vector (7 DOWNTO 0);

      cs_DUT       : OUT    std_logic;

      cs_vor       : OUT    std_logic;

      trig_monitor : OUT    std_logic

   );

-- Declarations

END Puls_Generator ;

--

-- VHDL Architecture FPGA_Box.Puls_Generator.fsm

--

-- Created:

--          by - chrebhu.UNKNOWN (CHSEM00-6-103)

--          at - 13:41:23 04.02.2014

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2010.3 (Build 21)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ARCHITECTURE fsm OF Puls_Generator IS