1 | /************************************************************************/
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2 | // Lauflicht Beispiel Nr. 1
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3 | // Datum: 01.05.2014
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4 | // Autor: Ingo Schick
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5 | /************************************************************************/
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6 |
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7 | /************************************************************************/
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8 | //Include Dateien
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9 | /************************************************************************/
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10 | #include <p18f46k80.h> // PIC18F46K80 auswählen
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11 | #include <stdio.h> // Standard-Bibiotheken einbeziehen
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12 | #include "SP_PIC18F46K80.H"
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13 | #include "Warten_MS.C"
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14 | /************************************************************************/
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15 |
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16 | /************************************************************************/
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17 | // Microcontroller-Konfiguration
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18 | /************************************************************************/
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19 | // CONFIG1L
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20 | #pragma config RETEN = OFF
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21 | #pragma config INTOSCSEL = LOW
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22 | #pragma config SOSCSEL = DIG
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23 | #pragma config XINST = OFF
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24 |
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25 | // CONFIG1H
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26 | #pragma config FOSC = HS2 // Oscillator (HS oscillator (Medium power, 16 MHz - 25 MHz))
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27 | #pragma config PLLCFG = OFF
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28 | #pragma config FCMEN = OFF
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29 | #pragma config IESO = OFF
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30 |
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31 | // CONFIG2L
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32 | #pragma config PWRTEN = OFF // Power Up Timer (Disabled)
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33 | #pragma config BOREN = OFF
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34 | #pragma config BORV = 3 // Brown-out Reset Voltage bits (1.8V)
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35 | #pragma config BORPWR = ZPBORMV // BORMV Power level (ZPBORMV instead of BORMV is selected)
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36 |
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37 | // CONFIG2H
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38 | #pragma config WDTEN = SWDTDIS // Watchdog Timer (WDT enabled in hardware; SWDTEN bit disabled)
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39 | #pragma config WDTPS = 1048576 // Watchdog Postscaler (1:1048576)
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40 |
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41 | // CONFIG3H
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42 | #pragma config CANMX = PORTC // ECAN Mux bit (ECAN TX and RX pins are located on RB2 and RB3, respectively)
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43 | #pragma config MSSPMSK = MSK7 // MSSP address masking (7 Bit address masking mode)
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44 | #pragma config MCLRE = ON // Master Clear Enable (MCLR Enabled, RG5 Disabled)
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45 |
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46 | // CONFIG4L
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47 | #pragma config STVREN = OFF // Stack Overflow Reset (Disabled)
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48 | #pragma config BBSIZ = BB2K // Boot Block Size (2K word Boot Block size)
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49 |
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50 | // CONFIG5L
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51 | #pragma config CP0 = OFF // Code Protect 00800-03FFF (Disabled)
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52 | #pragma config CP1 = OFF // Code Protect 04000-07FFF (Disabled)
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53 | #pragma config CP2 = OFF // Code Protect 08000-0BFFF (Disabled)
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54 | #pragma config CP3 = OFF // Code Protect 0C000-0FFFF (Disabled)
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55 |
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56 | // CONFIG5H
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57 | #pragma config CPB = OFF // Code Protect Boot (Disabled)
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58 | #pragma config CPD = OFF // Data EE Read Protect (Disabled)
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59 |
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60 | // CONFIG6L
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61 | #pragma config WRT0 = OFF // Table Write Protect 00800-03FFF (Disabled)
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62 | #pragma config WRT1 = OFF // Table Write Protect 04000-07FFF (Disabled)
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63 | #pragma config WRT2 = OFF // Table Write Protect 08000-0BFFF (Disabled)
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64 | #pragma config WRT3 = OFF // Table Write Protect 0C000-0FFFF (Disabled)
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65 |
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66 | // CONFIG6H
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67 | #pragma config WRTC = OFF // Config. Write Protect (Disabled)
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68 | #pragma config WRTB = OFF // Table Write Protect Boot (Disabled)
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69 | #pragma config WRTD = OFF // Data EE Write Protect (Disabled)
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70 |
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71 | // CONFIG7L
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72 | #pragma config EBTR0 = OFF // Table Read Protect 00800-03FFF (Disabled)
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73 | #pragma config EBTR1 = OFF // Table Read Protect 04000-07FFF (Disabled)
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74 | #pragma config EBTR2 = OFF // Table Read Protect 08000-0BFFF (Disabled)
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75 | #pragma config EBTR3 = OFF // Table Read Protect 0C000-0FFFF (Disabled)
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76 |
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77 | // CONFIG7H
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78 | #pragma config EBTRB = OFF // Table Read Protect Boot (Disabled)
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79 | /************************************************************************/
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80 |
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81 |
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82 | /************************************************************************/
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83 | // sonstige Deklarationen
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84 | /************************************************************************/
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85 | #define True 1
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86 | #define False 0
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87 | /************************************************************************/
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88 |
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89 | /************************************************************************/
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90 | // Hauptprogramm
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91 | /************************************************************************/
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92 |
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93 | void main(void)
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94 | {
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95 | char i;
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96 |
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97 | TRISB = 0x00;
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98 | PORTB = 0X00;
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99 |
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100 | TRISC= 0b01011000; // PORTC initalisieren
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101 | PORTC= 0b01011000;
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102 |
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103 | TRISD = 0x00;
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104 | PORTD = 0x00;
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105 |
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106 | //*****************************************************************************
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107 | // Start der Hauptprogramm-Schleife
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108 | //*****************************************************************************
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109 |
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110 | while(1) // Ganzes Programm ist Endlosschleife
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111 | {
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112 | for (i=0 ; i<7 ;i++)
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113 | {
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114 | PORTD = PORTD << 1;
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115 | Warten_MS(150);
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116 | }
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117 |
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118 | for (i=0 ; i<7 ;i++)
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119 | {
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120 | PORTD = PORTD >> 1;
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121 | Warten_MS(150);
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122 | }
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123 | }
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124 | //*****************************************************************************
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125 | } // Ende des Hauptprogramm
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126 | //*****************************************************************************
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