1 | void spi_fifo_init()
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2 | {
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3 | // Initialize SPI FIFO registers
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4 | SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI
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5 |
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6 | SpiaRegs.SPICCR.all=0x000F; //16-bit character, CLKPOL = 0
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7 | SpiaRegs.SPICTL.all=0x000A; //Interrupts off, CLKPH = 1, Talk = 1
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8 | SpiaRegs.SPISTS.all=0x0000;
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9 | SpiaRegs.SPIBRR=0x0063; // Baud rate UNUSED as SLAVE
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10 | SpiaRegs.SPIFFTX.all=0xC048; // Enable FIFO's, set TX FIFO level to 8
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11 | SpiaRegs.SPIFFRX.all=0x4061; // Set RX FIFO level to 1
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12 | SpiaRegs.SPIFFCT.all=0x00;
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13 | SpiaRegs.SPIPRI.all=0x0008;
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14 | SpiaRegs.SPIFFTX.bit.TXFFIENA=0; //TX Interrupt off
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15 | SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI
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16 |
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17 | SpiaRegs.SPIFFTX.bit.TXFIFO=1;
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18 | SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;
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19 | }
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20 |
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21 |
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22 | void InitSpiaGpio()
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23 | {
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24 |
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25 | EALLOW;
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26 |
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27 |
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28 | /* Enable internal pull-up for the selected pins */
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29 | // Pull-ups can be enabled or disabled by the user.
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30 | // This will enable the pullups for the specified pins.
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31 | // Comment out other unwanted lines.
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32 |
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33 | // GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
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34 | // GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
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35 | // GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA)
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36 | // GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA)
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37 |
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38 |
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39 | GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA)
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40 | GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA)
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41 | GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA)
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42 | GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA)
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43 |
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44 | GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; //Debug LED pull-up on
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45 | // GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; //SPI_Transfer pull-up on
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46 |
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47 | /*Direction of used GPIO*/
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48 | GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0;
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49 | GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1;
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50 | GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0;
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51 | GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0;
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52 |
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53 | /* Set qualification for selected pins to asynch only */
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54 | // This will select asynch (no qualification) for the selected pins.
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55 | // Comment out other unwanted lines.
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56 |
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57 | // GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
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58 | // GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
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59 | // GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
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60 | // GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)
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61 |
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62 | GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input (SPISIMOA)
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63 | GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input (SPISOMIA)
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64 | GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input (SPICLKA)
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65 | GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input (SPISTEA)
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66 |
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67 |
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68 | /* Configure SPI-A pins using GPIO regs*/
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69 | // This specifies which of the possible GPIO pins will be SPI functional pins.
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70 | // Comment out other unwanted lines.
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71 |
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72 | // GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
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73 | // GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
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74 | // GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
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75 | // GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA
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76 |
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77 | GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA
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78 | GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA
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79 | GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA
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80 | GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA
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81 |
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82 | GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0;// Configure GPIO1 as GPIO
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83 | GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 0;// Configure GPIO29 as GPIO
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84 |
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85 | /*Initial State! */
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86 | GpioDataRegs.GPACLEAR.bit.GPIO1=1;
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87 |
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88 | /*Direction of used GPIO*/
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89 | GpioCtrlRegs.GPADIR.bit.GPIO29 = 1; //GPIO Debug_LED out
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90 | GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; //GPIO SPI_Transfer out
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91 |
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92 |
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93 | EDIS;
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94 | }
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