Timer-Interrupt bei ATTiny2313 kommt nicht

[Jens K. (mister232)]

Ich versuche mich gerade an der Programmierung einer SPI-Schnittstelle 
mittels des USI-Interfaces eines ATTiny2313. Ich habe dazu Code von 
Atmel gefunden, welchen ich für meine Anwendung angepasst habe. Um den 
Clock zu erzeugen nutze ich den Timer0 mit dem Compare-Interrupt A. Hier 
die Initialisierung des SPI-Master und des Timers, wie gesagt, dass 
meiste ist von Atmel übernommen:

/*
 * SPI.c
 *
 * Created: 13.09.2004 12:08:54
 * Author: Atmel
 * Changed: 19.08.2014 17:48:49, J.Kathe
 *
 * Control and initialization functions for an USI SPI-Interface on an AVR. Written by Atmel
 */ 

#include "USI_SPI.h"
#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>

/* USI port and pin definitions.
 */
#define USI_OUT_REG  PORTB  //!< USI port output register.
#define USI_DIR_REG  DDRB  //!< USI port direction register.
#define USI_CLOCK_PIN  PB7  //!< USI clock I/O pin.
#define USI_DATAIN_PIN  PB5  //!< USI data input pin.
#define USI_DATAOUT_PIN  PB6  //!< USI data output pin.
#define USI_nSS_PIN PB4    //!< USI slave-select pin




/*  Speed configuration:
 *  Bits per second = CPUSPEED / PRESCALER / (COMPAREVALUE+1) / 2.
 *  Maximum = CPUSPEED / 64.
 */
#define TC0_PRESCALER_VALUE 256  //!< Must be 1, 8, 64, 256 or 1024.
#define TC0_COMPARE_VALUE   1  //!< Must be 0 to 255. Minimum 31 with prescaler CLK/1.




/*  Prescaler value converted to bit settings.
 */
#if TC0_PRESCALER_VALUE == 1
  #define TC0_PS_SETTING (1<<CS00)
#elif TC0_PRESCALER_VALUE == 8
  #define TC0_PS_SETTING (1<<CS01)
#elif TC0_PRESCALER_VALUE == 64
  #define TC0_PS_SETTING (1<<CS01)|(1<<CS00)
#elif TC0_PRESCALER_VALUE == 256
  #define TC0_PS_SETTING (1<<CS02)
#elif TC0_PRESCALER_VALUE == 1024
  #define TC0_PS_SETTING (1<<CS02)|(1<<CS00)
#else
  #error Invalid T/C0 prescaler setting.
#endif



/*! \brief  Data input register buffer.
 *
 *  Incoming bytes are stored in this byte until the next transfer is complete.
 *  This byte can be used the same way as the SPI data register in the native
 *  SPI module, which means that the byte must be read before the next transfer
 *  completes and overwrites the current value.
 */
unsigned char storedUSIDR;



/*! \brief  Driver status bit structure.
 *
 *  This struct contains status flags for the driver.
 *  The flags have the same meaning as the corresponding status flags
 *  for the native SPI module. The flags should not be changed by the user.
 *  The driver takes care of updating the flags when required.
 */
struct usidriverStatus_t {
  unsigned char masterMode : 1;       //!< True if in master mode.
  unsigned char transferComplete : 1; //!< True when transfer completed.
  unsigned char writeCollision : 1;   //!< True if put attempted during transfer.
};

volatile struct usidriverStatus_t spiX_status; //!< The driver status bits.



// Change for SPI-Slave!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
ISR(TIMER0_COMPA_vect)
{
  USICR |= (1<<USITC);  // Toggle clock output pin.
  
  //wait for next transmission
  PORTD |= (1<<PD4);
  _delay_ms(500);
  PORTD &= ~(1<<PD4);
  _delay_ms(500);
}



/*! \brief  USI Timer Overflow Interrupt handler.
 *
 *  This handler disables the compare match interrupt if in master mode.
 *  When the USI counter overflows, a byte has been transferred, and we
 *  have to stop the timer tick.
 *  For all modes the USIDR contents are stored and flags are updated.
 */
ISR( USI_OVERFLOW_vect )
{
  // Master must now disable the compare match interrupt
  // to prevent more USI counter clocks.
  if( spiX_status.masterMode == 1 ) {
    TIMSK &= ~(1<<OCIE0A);
  }
  
  // Update flags and clear USI counter
  USISR = (1<<USIOIF);
  spiX_status.transferComplete = 1;

  // Copy USIDR to buffer to prevent overwrite on next transfer.
  storedUSIDR = USIDR;
}



/*! \brief  Initialize USI as SPI master.
 *
 *  This function sets up all pin directions and module configurations.
 *  Use this function initially or when changing from slave to master mode.
 *  Note that the stored USIDR value is cleared.
 *
 *  \param spi_mode  Required SPI mode, must be 0 or 1.
 */
void spiX_initmaster( char spi_mode )
{
  // Configure port directions.
  USI_DIR_REG |= (1<<USI_DATAOUT_PIN) | (1<<USI_CLOCK_PIN) | (1<<USI_nSS_PIN); // Outputs.
  USI_DIR_REG &= ~(1<<USI_DATAIN_PIN);                      // Inputs.
  USI_OUT_REG |= (1<<USI_DATAIN_PIN);                       // Pull-ups.
  
  // Pull nSS up, so no slave is selected
  PORTB |= (1<<USI_nSS_PIN);
  
  // Configure USI to 3-wire master mode with overflow interrupt.
  USICR = (1<<USIOIE) | (1<<USIWM0) | (1<<USICS1) | (spi_mode<<USICS0) | (1<<USICLK);

  // Enable 'Clear Timer on Compare match' and init prescaler.
  TCCR0A |= (1<<WGM01) | (1<<WGM00);
  TCCR0B |= (1<<TC0_PS_SETTING);

  // Init Output Compare Register.
  OCR0A = TC0_COMPARE_VALUE;
  
  // Init driver status register.
  spiX_status.masterMode       = 1;
  spiX_status.transferComplete = 0;
  spiX_status.writeCollision   = 0;
  
  storedUSIDR = 0;
}



/*! \brief  Initialize USI as SPI slave.
 *
 *  This function sets up all pin directions and module configurations.
 *  Use this function initially or when changing from master to slave mode.
 *  Note that the stored USIDR value is cleared.
 *
 *  \param spi_mode  Required SPI mode, must be 0 or 1.
 */
void spiX_initslave( char spi_mode )
{
  // Configure port directions.
  USI_DIR_REG |= (1<<USI_DATAOUT_PIN); // Outputs.
  USI_DIR_REG &= ~(1<<USI_DATAIN_PIN) | (1<<USI_CLOCK_PIN) | ~(1<<USI_nSS_PIN); // Inputs.
  USI_OUT_REG |= (1<<USI_DATAIN_PIN) | (1<<USI_CLOCK_PIN) | (1<<USI_nSS_PIN);  // Pull-ups.
  
  // Configure USI to 3-wire slave mode with overflow interrupt.
  USICR = (1<<USIOIE) | (1<<USIWM0) | (1<<USICS1) | (spi_mode<<USICS0);
  
  // Init driver status register.
  spiX_status.masterMode       = 0;
  spiX_status.transferComplete = 0;
  spiX_status.writeCollision   = 0;
  
  storedUSIDR = 0;
}



/*! \brief  Put one byte on bus.
 *
 *  Use this function like you would write to the SPDR register in the native SPI module.
 *  Calling this function in master mode starts a transfer, while in slave mode, a
 *  byte will be prepared for the next transfer initiated by the master device.
 *  If a transfer is in progress, this function will set the write collision flag
 *  and return without altering the data registers.
 *
 *  \returns  0 if a write collision occurred, 1 otherwise.
 */
char spiX_put( unsigned char val )
{
  // Check if transmission in progress,
  // i.e. USI counter unequal to zero.
  if( (USISR & 0x0F) != 0 ) {
    // Indicate write collision and return.
    spiX_status.writeCollision = 1;
    return 0;
  }
  
  // Reinit flags.
  spiX_status.transferComplete = 0;
  spiX_status.writeCollision = 0;

  // Put data in USI data register.
  USIDR = val;
  
  // Pull nSS down, so slave is selected
  PORTB &= ~(1<<USI_nSS_PIN);
  
  // Master should now enable compare match interrupts.
  if( spiX_status.masterMode == 1 ) {
    TIFR |= (1<<OCF0A);   // Clear compare match flag.
    TIMSK |= (1<<OCIE0A); // Enable compare match interrupt.
  }

  if( spiX_status.writeCollision == 0 ) return 1;
  return 0;
}



/*! \brief  Get one byte from bus.
 *
 *  This function only returns the previous stored USIDR value.
 *  The transfer complete flag is not checked. Use this function
 *  like you would read from the SPDR register in the native SPI module.
 */
unsigned char spiX_get()
{
  return storedUSIDR;
}



/*! \brief  Wait for transfer to complete.
 *
 *  This function waits until the transfer complete flag is set.
 *  Use this function like you would wait for the native SPI interrupt flag.
 */
void spiX_wait()
{
  //do {} while( spiX_status.transferComplete == 0 );
    
  // Pull nSS up, so no slave is selected
  PORTB |= (1<<USI_nSS_PIN);
}



// end of file

Und hier noch die Main:

#include "USI_SPI.h"

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>

int main(void)
{
  unsigned short loopCNT;
  char val;
  
  // Initialize pin for LED
  DDRD |= (1<<PD4);
  
  // Initialize USI-Interface as SPI master
  spiX_initmaster(SPIMODE);
  
  // Global enable interrupts
  sei();
  
  // Toggle LED to check it
  for(loopCNT = 0; loopCNT < 3; loopCNT++)
  {
    PORTD |= (1<<PD4);
    _delay_ms(500);
    PORTD &= ~(1<<PD4);
    _delay_ms(500);
  }
  
  while(1)
    {
        spiX_put('1'); // Send data
    spiX_wait(); // Wait for transmission finished
    val = spiX_get();
    
    if(val == '1')
    {
      PORTD |= (1<<PD4);
    }
    else
    {
      PORTD &= ~(1<<PD4);
    }
    }
}

Ich lasse eine LED in der Interrupt-Routine des Timers blinken, um zu 
sehen ob er da überhaupt irgendwie reinkommt. Ich weiß, das hält den 
nächsten Interrupt auf und versaut das Timing, aber es ging erstmal nur 
darum zu sehen ob etwas passiert. Die LED macht aber gar nichts (außer 
am Anfang nach der Initialisierung).

[H.Joachim S. (crazyhorse)]

TIMSK?

[Jens K. (mister232)]

Wurde in spiX_put() realisiert und außerdem im Overflow-Interrupt der 
USI-Schnittstelle

[Marc V. (Firma: Vescomp) (logarithmus)]

Jens K. schrieb:
> // Enable 'Clear Timer on Compare match' and init prescaler.
>   TCCR0A |= (1<<WGM01) | (1<<WGM00);

 Das ist kein Compare match, sondern Fast PWM.