1 | #define MODBUS_ENABLED_DDR DDRA
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2 | #define MODBUS_ENABLED_PORT PORTA
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3 | #define MODBUS_ENABLED PA0
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4 | #define MODBUS_ENABLED_Output() MODBUS_ENABLED_DDR |= (1 << MODBUS_ENABLED)
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5 | #define MODBUS_ENABLED_HIGH() (MODBUS_ENABLED_PORT |= (1 << MODBUS_ENABLED))
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6 | #define MODBUS_ENABLED_LOW() (MODBUS_ENABLED_PORT &= ~(1 << MODBUS_ENABLED))
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7 | #define MODBUS_ENABLED_READ() MODBUS_ENABLED_LOW()
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8 | #define MODBUS_ENABLED_WRITE() MODBUS_ENABLED_HIGH()
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9 |
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10 |
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11 | int main(void)
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12 | {
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13 | uint32_t debug_tx_counter = 500000UL;
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14 |
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15 | //Timers_Init(); // Wird im Testprogramm nicht benutzt
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16 | Uart0_Init(19200);
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17 | MODBUS_ENABLED_Output();
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18 | MODBUS_ENABLED_READ();
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19 |
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20 | sei();
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21 |
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22 | while(1)
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23 | {
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24 | if(debug_tx_counter++ >= 200000UL)
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25 | {
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26 | debug_tx_counter = 0;
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27 | MODBUS_ENABLED_WRITE();
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28 | Uart0_Write(0xFF);
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29 | Uart0_Write(0x00);
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30 | Uart0_Write(0xAA);
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31 | Uart0_Write(0x0A);
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32 | }
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33 | }
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34 | }
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35 |
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36 | void Uart0_Init(unsigned long baud)
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37 | {
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38 | uint16_t _baud;
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39 |
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40 | // Standard Einstellungen vom IFC 050
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41 | // Baudrate 19200
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42 | // Daten bits 8
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43 | // Parity even
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44 | // Stop bits 1
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45 |
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46 | // Berechent aus der Baudrate den Register wert für die Baudrate
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47 | _baud = (F_CPU / 8 / baud - 1) / 2;
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48 |
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49 | // Setzt die Baudrate
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50 | UBRR0 = _baud;
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51 |
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52 | UCSR0B |= (1 << RXEN0); // Receiver Enable
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53 | UCSR0B |= (1 << TXEN0); // Transmitter Enable
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54 | UCSR0B |= (1 << RXCIE0); // RX Complete Interrupt Enable
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55 | //UCSR0B |= (1 << TXCIE0); // TX Complete Interrupt Enable
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56 | UCSR0B |= (1 << UDRIE0); // USART Data Register Empty Interrupt Enable
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57 |
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58 | // USART Mode of Operation
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59 | // ==========================================
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60 | // | UMSEL01 | UMSEL00 | Mode |
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61 | // ==========================================
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62 | // | 0 | 0 | Asynchronous USART |
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63 | // | 0 | 1 | Synchronous USART |
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64 | // | 1 | 0 | Reserved |
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65 | // | 1 | 1 | Master SPI |
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66 | // ==========================================
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67 | // Register Bits von: UCSR0C
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68 | // Quelle: Datenblatt ATtiny441/841 Seite 184
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69 | // SUSART Mode = Asynchronous
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70 |
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71 |
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72 | // Daten bits
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73 | // ================================================
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74 | // | UCSZ02 | UCSZ01 | UCSZ00 | Character Size |
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75 | // ================================================
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76 | // | 0 | 0 | 0 | 5-bit |
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77 | // | 0 | 0 | 1 | 6-bit |
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78 | // | 0 | 1 | 0 | 7-bit |
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79 | // | 0 | 1 | 1 | 8-bit |
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80 | // | 1 | 0 | 0 | Reserved |
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81 | // | 1 | 0 | 1 | Reserved |
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82 | // | 1 | 1 | 0 | Reserved |
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83 | // | 1 | 1 | 1 | 9-bit |
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84 | // ================================================
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85 | // Register Bits von: UCSR0C
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86 | // Quelle: Datenblatt ATtiny441/841 Seite 184
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87 | // Setzt Daten bits = 8-bit.
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88 | UCSR0C |= ((1 << UCSZ01) | (1 << UCSZ00));
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89 |
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90 | // Parity
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91 | // =========================================
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92 | // | UPM01 | UPM00 | Parity Mode |
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93 | // =========================================
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94 | // | 0 | 0 | Disabled |
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95 | // | 0 | 1 | Reserved |
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96 | // | 1 | 0 | Enabled, Even Parity |
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97 | // | 1 | 1 | Enabled, Odd Parity |
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98 | // =========================================
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99 | // Register Bits von: UCSR0C
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100 | // Quelle: Datenblatt ATtiny441/841 Seite 184
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101 | // Setzt Parity = Even.
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102 | UCSR0C |= (1 << UPM01);
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103 |
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104 | // Stop bits
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105 | // ========================
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106 | // | USBS0 | Stop Bit(s) |
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107 | // ========================
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108 | // | 0 | 1-bit |
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109 | // | 1 | 2-bit |
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110 | // ========================
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111 | // Register Bits von: UCSR0C
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112 | // Quelle: Datenblatt ATtiny441/841 Seite 184
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113 | // Setzt Stop bits = 1-bit
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114 |
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115 | // Clock Polarity Settings
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116 | // =============================================================
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117 | // | UCPOL | Transmitted Data Changed | Received Data Sampled |
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118 | // | | (Output of TxDn Pin) | (Input on RxDn Pin) |
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119 | // =============================================================
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120 | // | 0 | Rising XCK Edge | Falling XCK Edge |
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121 | // | 1 | Falling XCK Edge | Rising XCK Edge |
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122 | // =============================================================
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123 | // Register Bits von: UCSR0C
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124 | // Quelle: Datenblatt ATtiny441/841 Seite 185
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125 | // Clock Polarity := Tx=Rising XCK Edge, Rx=Falling XCK Edge
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126 | }
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