1 | // PIC18F2550 Configuration Bit Settings
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2 |
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3 | // 'C' source line config statements
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4 |
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5 | #include <xc.h>
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6 |
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7 | // #pragma config statements should precede project file includes.
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8 | // Use project enums instead of #define for ON and OFF.
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9 |
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10 | // CONFIG1L
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11 | #pragma config PLLDIV = 1 // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
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12 | #pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
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13 | #pragma config USBDIV = 1 // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)
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14 |
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15 | // CONFIG1H
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16 | #pragma config FOSC = INTOSCIO_EC// Oscillator Selection bits (Internal oscillator, port function on RA6, EC used by USB (INTIO))
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17 | #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
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18 | #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
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19 |
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20 | // CONFIG2L
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21 | #pragma config PWRT = ON // Power-up Timer Enable bit (PWRT enabled)
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22 | #pragma config BOR = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
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23 | #pragma config BORV = 3 // Brown-out Reset Voltage bits (Minimum setting)
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24 | #pragma config VREGEN = OFF // USB Voltage Regulator Enable bit (USB voltage regulator disabled)
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25 |
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26 | // CONFIG2H
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27 | #pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
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28 | #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
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29 |
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30 | // CONFIG3H
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31 | #pragma config CCP2MX = ON // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
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32 | #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
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33 | #pragma config LPT1OSC = OFF // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
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34 | #pragma config MCLRE = OFF // MCLR Pin Enable bit (RE3 input pin enabled; MCLR pin disabled)
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35 |
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36 | // CONFIG4L
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37 | #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
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38 | #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
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39 | #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
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40 |
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41 | // CONFIG5L
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42 | #pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
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43 | #pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
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44 | #pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
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45 | #pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)
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46 |
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47 | // CONFIG5H
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48 | #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
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49 | #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
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50 |
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51 | // CONFIG6L
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52 | #pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
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53 | #pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
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54 | #pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
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55 | #pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
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56 |
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57 | // CONFIG6H
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58 | #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
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59 | #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
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60 | #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
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61 |
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62 | // CONFIG7L
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63 | #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
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64 | #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
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65 | #pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
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66 | #pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
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67 |
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68 | // CONFIG7H
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69 | #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
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