1 | #include "GLOBALVARIABLE.ASM"
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2 | ;-------------------------------------------------------------------------------
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3 | RSEG CSTACK ; Define stack segment
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4 | ;-------------------------------------------------------------------------------
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5 | RSEG CODE ; Assemble to Flash memory
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6 | ;-----------------------------------------------------------------------------
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7 | IMPORT PROSSEDUR1_INIT
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8 | IMPORT PROSSEDUR2_INIT
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9 | ;******************************************************************************
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10 | ; MSP430x261x Demo - Timer_A, Toggle P1.0, TACCR0 Cont. Mode ISR, DCO SMCLK
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11 | ; Description: Toggle P1.0 using software and TA_0 ISR. Toggles every
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12 | ; 50000 SMCLK cycles. SMCLK provides clock source for TACLK.
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13 | ; During the TA_0 ISR, P1.0 is toggled and 50000 clock cycles are added
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14 | ; to TACCR0. TA_0 ISR is triggered every 50000 cycles. CPU is normally off
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15 | ; and used only during TA_ISR.
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16 | ; ACLK = 32.768kHz, MCLK = SMCLK = TACLK = default DCO
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17 | ;
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18 | ; MSP430F241x
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19 | ; MSP430F261x
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20 | ; -----------------
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21 | ; /|\| XIN|-
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22 | ; | | | 32kHz
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23 | ; --|RST XOUT|-
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24 | ; | |
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25 | ; | P1.0|-->LED
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26 | ;
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27 | ; Bhargavi Nisarga
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28 | ; Texas Instruments Inc.
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29 | ; September 2007
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30 | ; Built with IAR Embedded Workbench Version: 3.47A
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31 | ;****************************************************************************
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32 |
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33 | RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
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34 | StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
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35 |
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36 | OFIFGcheck bic.b #OFIFG,&IFG1 ; Clear OFIFG
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37 | mov.w #047FFh,R15 ; Wait for OFIFG to set again if
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38 | OFIFGwait dec.w R15 ; not stable yet
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39 | jnz OFIFGwait
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40 | bit.b #OFIFG,&IFG1 ; Has it set again?
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41 | jnz OFIFGcheck ; If so, wait some more
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42 |
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43 |
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44 | SetupP5 bis.b #BIT0,&P1DIR ; P1.0 output
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45 | mov.w #0,r12
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46 | SetupC0 mov.w #CCIE,&TACCTL0 ; TACCR0 interrupt enabled
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47 | mov.w #50000,&TACCR0 ;
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48 | SetupTA mov.w #TASSEL_2+MC_2,&TACTL ; SMCLK, continuous mode
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49 | SetPort call #PROSSEDUR1_INIT
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50 | call #PROSSEDUR2_INIT
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51 | ;
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52 | Mainloop bis.w #CPUOFF+GIE,SR ; CPU off, interrupts enabled
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53 | nop ; Required for debugger
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54 | TESTVALUE: ;
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55 | call #HAUPT_ROUTIN
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56 | clr r12
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57 | ret
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58 | ;
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59 | ;------------------------------------------------------------------------------
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60 | TA0_ISR; Toggle P1.0
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61 | ;----------------------------------------------------------------------------
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62 | inc r12 ;einzähler incrementieren
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63 | cmp #20,r12
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64 | jeq TESTVALUE ; wenn das stimmt
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65 | reti ;
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66 |
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67 | ;----------------------------------------------------------------------------
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68 | COMMON INTVEC ; Interrupt Vectors
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69 | ;----------------------------------------------------------------------------
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70 | ORG RESET_VECTOR ; MSP430 RESET Vector
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71 | DW RESET ;
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72 | ORG TIMERA0_VECTOR ; Timer_A0 Vector
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73 | DW TA0_ISR ;
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74 | END
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