1 | #ifndef CONF_CLOCK_H_INCLUDED
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2 | #define CONF_CLOCK_H_INCLUDED
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3 |
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4 | // ===== System Clock (MCK) Source Options
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5 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC
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6 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL
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7 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS
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8 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
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9 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC
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10 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC
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11 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL
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12 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS
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13 | #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
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14 |
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15 | // ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))
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16 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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17 | #define CONFIG_SYSCLK_PRES SYSCLK_PRES_2
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18 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4
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19 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8
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20 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16
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21 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32
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22 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64
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23 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3
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24 |
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25 | // ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
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26 | // Use mul and div effective values here.
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27 | #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
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28 | #define CONFIG_PLL0_MUL 16
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29 | //#define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)
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30 | #define CONFIG_PLL0_DIV 1
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31 |
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32 | // Fbus = Fsys / BUS_div
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33 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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34 |
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35 |
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36 | // ===== USB Clock Source Options (Fusb = FpllX / USB_div)
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37 | // Use div effective value here.
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38 | #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
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39 | #define CONFIG_USBCLK_DIV 2
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40 |
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41 | // ===== Target frequency (System clock)
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42 | // - XTAL frequency: 12MHz
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43 | // - System clock source: PLLA
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44 | // - System clock prescaler: 2 (divided by 2)
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45 | // - PLLA source: XTAL
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46 | // - PLLA output: XTAL * 16 / 1
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47 | // - System clock: 12 * 16 / 1 / 2 = 96MHz
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48 | // ===== Target frequency (USB Clock)
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49 | // - USB clock source: PLLA
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50 | // - USB clock divider: 2 (divided by 2)
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51 | // - PLLA output: XTAL * 16 / 2
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52 | // - USB clock: 12 * 16 / 2 / 2 = 48MHz
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53 |
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54 |
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55 | #endif /* CONF_CLOCK_H_INCLUDED */
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