1 | //----------------------------------------------------------------------------
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2 | // control register bit definitions for DDS
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3 | // Register 16Bit
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4 | //
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5 | // DB15|DB14|DB13|DB12|DB11|DB10|DB9|DB8| |DB7|DB6|DB5|DB4|DB3|DB2|DB1|DB0|
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6 | // 0 | 0 | B28| HLB|FSEL|PSEL| 0 |RST| |SL1|SL2|OPB| 0 |DV2| 0 |MOD| 0 |
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7 | //----------------------------------------------------------------------------
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8 | #define B28 13
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9 | #define HLB 12
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10 | #define FSELECT 11
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11 | #define PSELECT 10
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12 | #define DDRESET 8
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13 | #define SLEEP1 7
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14 | #define SLEEP2 6
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15 | #define OPBITEN 5
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16 | #define DIV2 3
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17 | #define MODE 1
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18 |
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19 | #define OFF 0
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20 | #define ON 1
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21 | #define SINE 3
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22 | #define TRI 4
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23 | #define REC 5
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24 | #define REC2 6
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25 |
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26 |
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27 | //----------------------------------------------------------------------------
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28 | // Chip select for SPI data of DDS
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29 | //----------------------------------------------------------------------------
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30 | #define CS_AD9833 B,2
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31 |
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32 | //----------------------------------------------------------------------------
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33 | // ATMEGA88 SPI
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34 | //----------------------------------------------------------------------------
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35 | #define P_MOSI B,3
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36 | #define P_MISO B,4
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37 | #define P_SCK B,5
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38 | #define P_SS B,2
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39 |
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40 | //Debug Port
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41 | #define DBG B,1
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42 |
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43 | // Prototypes
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44 | void spi_init(void);
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45 | void DDS_write(uint16_t data);
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46 | void DDS_reset(void);
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47 | void DDS_freq(uint32_t frq);
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48 | void DDS_signal(uint8_t mode);
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49 |
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50 |
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51 | // current state bites of control register
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52 | static uint16_t state = 0;
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53 |
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54 | int
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55 | main(void) {
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56 |
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57 | _delay_ms(1000); // only for debugging
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58 | SET(DBG);
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59 | SET_OUTPUT(DBG); // Marker to trigger logic analyser
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60 |
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61 | spi_init();
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62 | DDS_reset();
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63 | DDS_freq(400);
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64 | DDS_signal(SINE);
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65 |
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66 | // MAIN loop
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67 | while(1) {
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68 |
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69 | }
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70 | }
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71 |
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72 |
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73 | void
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74 | spi_init(void) {
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75 |
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76 |
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77 | // init SS to ensure SPI will work!
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78 | SET(P_SS);
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79 | SET_OUTPUT(P_SS);
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80 |
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81 | RESET(P_SCK);
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82 | RESET(P_MOSI);
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83 | RESET(P_MISO);
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84 |
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85 | SET_OUTPUT(P_SCK);
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86 | SET_OUTPUT(P_MOSI);
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87 | SET_INPUT(P_MISO);
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88 |
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89 | // activate SPI, set master, MODE 2 (CPHA=0,CPOL=1) , fosc/16
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90 | SPCR = (1<<SPE) | (1<<MSTR) | (1<<CPOL) | (1<<SPR0);
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91 |
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92 | }
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93 |
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94 |
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95 | void
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96 | DDS_write(uint16_t data) {
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97 |
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98 |
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99 | RESET(CS_AD9833);
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100 |
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101 | SPDR = (uint8_t)(data >> 8); //Left 8 Bit
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102 | while( !( SPSR & (1<<SPIF) ) );
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103 |
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104 | SPDR = (uint8_t)data; //Right 8 Bit
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105 | while( !( SPSR & (1<<SPIF) ) );
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106 |
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107 | SET(CS_AD9833);
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108 | }
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109 |
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110 | void
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111 | DDS_reset(void) {
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112 |
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113 | state = (1<<B28) | (1<<DDRESET) | (1<<SLEEP1) | (1<<OPBITEN) | (1<<MODE);
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114 | DDS_write(state);
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115 | state &= ~(1<<DDRESET);
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116 | _delay_ms(1);
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117 | DDS_write(state);
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118 | }
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119 |
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120 |
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121 | void
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122 | DDS_freq(uint32_t frq) {
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123 |
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124 | //calculate FREQ register value
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125 | //for given frequence in Hz
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126 | // 2^28 / 4194304Mhz = 64
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127 | uint32_t regval = frq * 64;
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128 |
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129 | //Split 32Bit value in two 14Bit transfers
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130 | //D15 and D14 define the frequency register.
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131 | //Fixed to D15 D14 = 01 means using FREQ0
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132 | DDS_write(0x4000 | (regval & 0x3FFF));
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133 | DDS_write(0x4000 | ((uint32_t)(regval >> 14) & 0x3FFFL));
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134 | }
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135 |
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136 | void
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137 | DDS_signal(uint8_t mode) {
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138 |
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139 | switch(mode) {
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140 |
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141 | case OFF:
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142 | state |= (1<<SLEEP1);
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143 | break;
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144 | case ON:
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145 | state &= ~(1<<SLEEP1);
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146 | break;
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147 | case SINE:
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148 | state &= ~((1<<OPBITEN) | (1<<MODE) | (1<<SLEEP1));
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149 | break;
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150 | case REC2:
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151 | state &= ~((1<<MODE) | (1<<DIV2) | (1<<SLEEP1));
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152 | state |= (1<<OPBITEN);
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153 | break;
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154 | case REC:
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155 | state |= (1<<OPBITEN) | (1<<DIV2);
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156 | state &= ~((1<<MODE) | (1<<SLEEP1));
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157 | break;
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158 | case TRI:
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159 | state &= ~((1<<OPBITEN) | (1<<SLEEP1));
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160 | state |= (1<<MODE);
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161 | break;
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162 | default:
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163 | state |= (1<<OPBITEN) | (1<<MODE);
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164 | }
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165 |
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166 | DDS_write(state);
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167 | }
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