Probleme mit Verzögerungsmodell: Transport

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity problem is

end entity problem;

architecture behavioral of problem is

  signal clk      : std_logic := '1';

  signal test_sig : std_logic := '0';

  signal reg      : std_logic := '0';

  signal reg_r    : std_logic := '0';

  constant clk_period : time := 10 ns;

begin  -- architecture behavioral

  clk <= not clk after clk_period/2;

  test_sig <= '0' after 0 ns,

              '1' after 20*clk_period;

  reg <= transport test_sig after 10*clk_period;

  process(clk)

  begin

    if rising_edge(clk) then

      reg_r <= reg;

    end if;

  end process;

end architecture behavioral;