Xilinx Vivado LVDS RX DPA (dynamic phase alignment)

  -----------------------------------------------------------------------------

  IBD : IBUFDS

    generic map (

      DQS_BIAS => "FALSE"               -- (FALSE, TRUE)

      )

    port map (

      O  => RxxD(i),                    -- 1-bit output: Buffer output

      I  => LvdsRxxDI_p(i),             -- 1-bit input: Diff_p buffer input (connect to top-level port)

      IB => LvdsRxxDI_n(i)              -- 1-bit input: Diff_n buffer input (connect to top-level port)

      );

  -----------------------------------------------------------------------------

  ISD : ISERDESE3

    generic map (

      DATA_WIDTH        => 8,           -- Parallel data width (4,8)

      FIFO_ENABLE       => "FALSE",     -- Enables the use of the FIFO

      FIFO_SYNC_MODE    => "FALSE",     -- Enables the use of internal 2-stage synchronizers on the FIFO

      IS_CLK_B_INVERTED => '0',         -- Optional inversion for CLK_B

      IS_CLK_INVERTED   => '1',         -- Optional inversion for CLK

      IS_RST_INVERTED   => '0',         -- Optional inversion for RST

      SIM_DEVICE        => "ULTRASCALE" -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS_ES1)

      )

    port map (

      FIFO_EMPTY  => open,              -- 1-bit output: FIFO empty flag

      Q           => RxParxD((8*i)+7 downto (8*i)),           -- 8-bit registered output

      CLK         => RxxC,              -- 1-bit input: High-speed clock

      CLK_B       => RxxC,              -- 1-bit input: Inversion of High-speed clock CLK

      CLKDIV      => LocxC,             -- 1-bit input: Divided Clock

      D           => RxxD(i),           -- 1-bit input: Serial Data Input

      FIFO_RD_CLK => '0',               -- 1-bit input: FIFO read clock

      FIFO_RD_EN  => '0',               -- 1-bit input: Enables reading the FIFO when asserted

      RST         => ResLvdsxR          -- 1-bit input: Asynchronous Reset

      );

  ---------------------------------------------------------------------------