1 | /*
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2 | * This example sets up the UART to send data to and receive data from the laptop
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3 | * When the data is received, an interrupt occurs and the data will then be taken from the buffer
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4 | */
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5 | #include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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6 | __interrupt void UART_isr(void);
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7 |
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8 | void scia_init();
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9 | void scia_xmit(int a);
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10 | void scia_msg(char *msg);
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11 | Uint16 bla;
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12 | Uint16 ReceivedChar;
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13 | char *msg;
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14 |
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15 | #define UART_MAXSTRLEN 10
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16 | volatile Uint16 uart_str_complete = 0; // 1 .. String komplett empfangen
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17 | volatile Uint16 uart_str_count = 0;
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18 | volatile char uart_string[UART_MAXSTRLEN + 1] = "";
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19 |
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20 |
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21 |
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22 | void main(void) {
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23 |
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24 | ReceivedChar=0;
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25 | bla=0;
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26 |
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27 | // Step 1: Setting the PLL, Watchdog, enable peripheral clocks
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28 | InitSysCtrl();
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29 |
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30 | // Step 3: Initialize the PIE control registers
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31 | // DINT; // Only necessary here if InitPieCtrl() does not have DINT; included
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32 | InitPieCtrl();
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33 |
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34 | IER = 0x0000;
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35 | IFR = 0x0000;
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36 |
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37 | // Step 4: Initialize the PIE vector table to default ISR
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38 | InitPieVectTable();
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39 |
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40 | // Configure the interrupt handling
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41 | // Setting up the XINT1 trigger, Table 112
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42 | EALLOW;
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43 | PieVectTable.SCIRXINTA = &UART_isr;
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44 | EDIS;
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45 |
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46 | // Enable XINT1 in the PIE
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47 | // PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enables the PIE interrupt table. Already done in InitPieVectTable();
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48 | PieCtrlRegs.PIEIER9.bit.INTx1 = 1; // Figure 87
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49 | IER |= M_INT9; // Sets the interrupt enable bit of group 9
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50 | EINT; // Enable global interrupts INTM
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51 | // Step 5: Initialize other device peripherals
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52 |
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53 | // We need to initialize our SCI
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54 | InitSciGpio();
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55 |
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56 | // Step 6: Write your code
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57 | scia_init(); // Initialize Sci FIFO
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58 | msg = "\r\nHello Alexander!\0";
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59 | scia_msg(msg);
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60 |
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61 | msg = "\r\nHow are you?\0";
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62 | scia_msg(msg);
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63 |
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64 | for(;;)
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65 | {
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66 | // Wait for inc character
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67 | while(SciaRegs.SCIFFRX.bit.RXFFST !=1) { } // wait for XRDY =1 for empty state
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68 | }
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69 | }
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70 |
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71 | void scia_init()
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72 | {
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73 | /*
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74 | * FIFO configuration
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75 | */
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76 | // SCIFFTX registers
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77 | SciaRegs.SCIFFTX.bit.SCIRST = 1; // Sci reset
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78 | SciaRegs.SCIFFTX.bit.SCIFFENA = 1; // Sci enhancements enabled
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79 | SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1; // Re-enable transmit FIFO operation
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80 | SciaRegs.SCIFFTX.bit.TXFFST = 0; // Transmit FIFO is empty
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81 | SciaRegs.SCIFFTX.bit.TXFFINTCLR = 1; // Clears TXFFINT flag
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82 | SciaRegs.SCIFFTX.bit.TXFFIENA = 0; // TX FIFO interrupt is disabled
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83 |
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84 | // SCIFFRX registers
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85 | SciaRegs.SCIFFRX.bit.RXFIFORESET = 1; // Re-enable receive FIFO operation
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86 | SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clears RXFFINT flag
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87 | SciaRegs.SCIFFRX.bit.RXFFIENA = 1; // RX FIFO interrupt is enabled
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88 | // SciaRegs.SCIFFRX.bit.RXFFIL = 0x1F; // 1111
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89 |
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90 | // SCIFFCT registers
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91 | SciaRegs.SCIFFCT.all = 0; // Lets leave it as it is for now
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92 |
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93 | /*
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94 | * Echoback configuration
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95 | */
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96 | // SCICCR registers
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97 | SciaRegs.SCICCR.bit.STOPBITS = 0; // 1 stop bit
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98 | SciaRegs.SCICCR.bit.PARITY = 0; // Odd Parity - but will be disabled anyways
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99 | SciaRegs.SCICCR.bit.PARITYENA = 0; // Parity disabled
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100 | SciaRegs.SCICCR.bit.LOOPBKENA = 0; // Loopback test mode disabled
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101 | SciaRegs.SCICCR.bit.ADDRIDLE_MODE = 0; // Idle line mode
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102 | SciaRegs.SCICCR.bit.SCICHAR = 7; // 8 char bits
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103 |
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104 | // SCICTL1 registers
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105 | SciaRegs.SCICTL1.bit.RXERRINTENA = 0; // Receive error interrupt disabled
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106 | SciaRegs.SCICTL1.bit.SWRESET = 0; // Initializing operating flags to the reset condition
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107 | SciaRegs.SCICTL1.bit.TXWAKE = 0; // Wake-up mode disabled
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108 | SciaRegs.SCICTL1.bit.SLEEP = 0; // Sleep mode disabled
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109 | SciaRegs.SCICTL1.bit.TXENA = 1; // Enable transmitter
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110 | SciaRegs.SCICTL1.bit.RXENA = 1; // Enable receiver
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111 |
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112 | // SCICTL2 registers
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113 | SciaRegs.SCICTL2.bit.TXRDY = 0; // SCITXBUF is full
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114 | SciaRegs.SCICTL2.bit.TXEMPTY = 0; // Transmitter buffer is loaded with data
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115 | SciaRegs.SCICTL2.bit.RXBKINTENA = 1; // Receiver buffer interrupt enabled
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116 | SciaRegs.SCICTL2.bit.TXINTENA = 1; // TXRDY interrupt enabled
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117 |
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118 | // SCIHBAUD registers for BAUD rate
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119 | SciaRegs.SCIHBAUD =0x0001; // 9600 baud @LSPCLK = 37.5MHz.
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120 | SciaRegs.SCILBAUD =0x00E7;
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121 |
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122 | // SCICTL1 registers again
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123 | SciaRegs.SCICTL1.all = 0x0023; // WTF?
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124 | }
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125 |
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126 | void scia_xmit(int a)
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127 | {
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128 | // Wait until sending is possible
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129 | while(SciaRegs.SCIFFTX.bit.TXFFST != 0) {}
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130 | SciaRegs.SCITXBUF = a; // Sending the data
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131 | bla=a-'0';
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132 | }
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133 |
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134 | void scia_msg(char * msg)
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135 | {
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136 | //
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137 | int i;
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138 | i = 0;
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139 | while(msg[i] != '\0')
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140 | {
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141 | //
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142 | scia_xmit(msg[i]);
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143 | i++;
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144 | }
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145 | }
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146 |
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147 | __interrupt void UART_isr(void)
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148 | {
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149 | // Get character
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150 | ReceivedChar = SciaRegs.SCIRXBUF.all;
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151 | if( uart_str_complete == 0 ) { // wenn uart_string gerade in Verwendung, neues Zeichen verwerfen
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152 |
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153 | // Daten werden erst in uart_string geschrieben, wenn nicht String-Ende/max Zeichenlänge erreicht ist/string gerade verarbeitet wird
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154 | if( ReceivedChar != '\n' &&
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155 | ReceivedChar != '\r' &&
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156 | uart_str_count < UART_MAXSTRLEN ) {
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157 | uart_string[uart_str_count] = ReceivedChar;
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158 | uart_str_count++;
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159 | }
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160 | else {
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161 | uart_string[uart_str_count] = '\0';
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162 | uart_str_count = 0;
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163 | uart_str_complete = 1;
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164 | }
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165 | }
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166 | msg = "\r\nYou sent: \0";
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167 | scia_msg(msg);
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168 | scia_xmit(ReceivedChar);
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169 |
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170 | SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
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171 | SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clears RXFFINT flag to enable new incoming interrupts
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172 | // Acknowledge this interrupt to get more from group 1
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173 | PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
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174 | }
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