Hallo Leute,
ich bin gerade am Verzweifeln. Seit stunden versuche ich vergeblichst,
den Strichpunktfehler zu finden, den mir Modelsim ausgibt. Langsam
glaube ich, dass es sich nicht um einen Strichpunkt Fehler handelt und
deshalb hoffe ich, ihr könntet mir helfen.
1 | library IEEE;
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2 | use IEEE.std_logic_1164.all;
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3 |
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4 | architecture struc of johnson_cnt is
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5 | signal s_inv_msb : std_logic;
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6 | signal s_load : std_logic;
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7 | signal s_q_intern : std_logic_vector(BITS - 1 downto 0);
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8 |
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9 | component dff_l
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10 | port(Clk : in std_logic;
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11 | Reset : in std_logic;
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12 | Load : in std_logic;
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13 | D_load : in std_logic;
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14 | D_in : in std_logic;
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15 | Q : out std_logic);
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16 | end component;
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17 |
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18 | component kor_sn
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19 | port(Msb_i : in std_logic;
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20 | Lsb_i : in std_logic;
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21 | Inv_msb : out std_logic;
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22 | Load_o : out std_logic);
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23 | end component;
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24 |
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25 | begin
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26 |
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27 | i_johnson_cnt : kor_sn
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28 | port map
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29 | (Msb_i => s_q_intern(BITS - 1),
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30 | Lsb_i => s_q_intern(0),
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31 | Inv_msb => s_inv_msb,
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32 | Load_o => s_load);
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33 |
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34 | i_johnson_cnt0 : for i in 0 to BITS - 1 generate
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35 | DFF_A : if i = 0 generate
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36 | I_0 : dff_l
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37 | port map
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38 | (Clk => Clk,
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39 | Reset => Reset,
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40 | Load => s_load,
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41 | D_load => D_load(i),
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42 | D_in => s_inv_msb,
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43 | Q => s_q_intern(i));
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44 | end generate DFF_A;
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45 |
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46 | DFF_M : if i > 0 and i < BITS - 1 generate
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47 | I_M : dff_l
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48 | port map
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49 | (Clk => Clk,
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50 | Reset => Reset,
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51 | Load => s_load,
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52 | D_load => D_load(i),
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53 | D_in => s_q_intern(i - 1),
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54 | Q => s_q_intern(i));
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55 | end generate DFF_M;
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56 |
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57 | DFF_E : if i = BITS - 1 generate
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58 | I_E : dff_l
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59 | port map
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60 | (Clk => Clk,
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61 | Reset => Reset,
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62 | Load => s_load,
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63 | D_load => D_load(i),
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64 | D_in => s_q_intern(i - 1),
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65 | Q => s_q_intern(i));
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66 | end generate DFF_E;
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67 |
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68 | Q_out <= s_q_intern;
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69 |
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70 | end architecture struc;
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Die Fehlermeldung, die ich erhalte, lautet:
near "architecture": expecting ';'
und es zeigt auf die letzte Architecture Zeile
1 | end architecture struc;
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