1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 |
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5 | entity test_1 is
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6 |
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7 | port(
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8 |
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9 | LEDR: out std_logic_vector(9 downto 0);
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10 | KEY: in std_logic_vector(3 downto 0);
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11 | SW: in std_logic_vector(9 downto 0);
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12 | ------------------------
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13 | AUD_BCLK: out std_logic;
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14 | AUD_XCK: out std_logic;
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15 | AUD_ADCLRCK: out std_logic;
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16 | AUD_ADCDAT: in std_logic;
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17 | AUD_DACLRCK: out std_logic;
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18 | AUD_DACDAT: out std_logic;
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19 | ------------------
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20 | FPGA_I2C_SCLK: out std_logic;
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21 | FPGA_I2C_SDAT: inout std_logic;
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22 | -------------------------
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23 | CLOCK_50 : in std_logic
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24 | );
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25 | end test_1;
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26 |
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27 |
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28 | architecture main of test_1 is
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29 | signal single_shot: std_logic:='0';
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30 | signal spi_clk_en: std_logic:='0';
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31 | signal clk_codec:std_logic:='0';
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32 | signal aud_prsc: integer range 0 to 255:=0;
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33 | signal codec_prsc: integer range 0 to 10 :=0;
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34 | signal data_H: std_logic_vector( 6 downto 0);
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35 | signal data_L: std_logic_vector( 8 downto 0);
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36 | signal input_index: integer range 0 to 31:=0;
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37 | signal rec_flag: std_logic:='0';
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38 | signal datain: std_logic_vector(31 downto 0):=(others=>'0');
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39 | signal clk_SPI: std_logic:='0';
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40 | signal spi_presc: integer range 0 to 50000000:=0;
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41 | signal spi_addr: std_logic_vector(7 downto 0):="00110100";
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42 | signal data_index: integer range 0 to 15:=0;
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43 | signal data_out: std_logic_vector(15 downto 0);
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44 | type fsm is (send_addr,ack1,ack2,ack3,data_high,data_low,sby,start, stop);
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45 | signal SPI_flag: std_logic:='0';
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46 | signal fsm_spi: fsm:=sby;
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47 |
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48 | begin
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49 | AUD_XCK<=clk_codec;
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50 | AUD_BCLK<=clk_codec;
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51 | data_out(15 downto 9)<=data_H;
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52 | data_out(8 downto 0)<=data_L;
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53 |
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54 |
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55 | process (CLOCK_50)
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56 | begin
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57 | if rising_edge(cloCK_50) then
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58 | ---------------SPI clock----------------------
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59 | if(spi_presc<5000)then
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60 | spi_presc<=spi_presc+1;
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61 | else
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62 | Clk_SPI<=not CLK_SPI;
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63 | spi_presc<=0;
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64 | end if;
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65 | ------------------CODEC clock-----------------
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66 | if(codec_prsc<4)then
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67 | codec_prsc<=codec_prsc+1;
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68 | else
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69 | codec_prsc<=0;
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70 | clk_codec<=not clk_codec;
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71 | end if;
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72 | ----------------------------------------------
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73 |
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74 | IF (spi_clk_en='1')then
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75 | FPGA_I2C_SCLK<= not clk_SPI;
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76 | else
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77 | FPGA_I2C_SCLK<='1';
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78 | end if;
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79 |
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80 |
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81 | end if;
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82 | end process;
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83 |
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84 | ----------------------SPI-FSM-----------------
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85 | process (clk_SPI)
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86 | begin
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87 |
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88 | if rising_edge(clk_SPI) then
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89 | if (SW(1)='1') then---hard reset
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90 | fsm_spi<=sby;
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91 | end if;
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92 |
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93 | case fsm_spi is
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94 | when send_addr=>
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95 | -----sende Adresse-----------------
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96 | spi_clk_en<='1';
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97 | LEDR(9 downto 6)<="0011";
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98 | if(data_index>0)then
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99 | FPGA_I2C_SDAT<=spi_addr(data_index);
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100 | data_index<=data_index-1;
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101 | else
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102 | FPGA_I2C_SDAT<=spi_addr(data_index);
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103 | data_index<=15;--- data length
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104 | fsm_spi<=ack1;
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105 | end if;
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106 | when ack1=>
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107 | ------------warte auf ACK-------------------
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108 | LEDR(9 downto 6)<="0100";
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109 | FPGA_I2C_SDAT<='Z';
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110 | if(FPGA_I2C_SDAT='0')then
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111 | fsm_spi<=data_high;
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112 | end if;
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113 | when data_high=>
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114 | ---------sende erste 8 bits und warte auf ACK----------
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115 | LEDR(9 downto 6)<="0101";
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116 | if(data_index>7)then
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117 | FPGA_I2C_SDAT<=data_out(data_index);
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118 | data_index<=data_index-1;
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119 | else
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120 | FPGA_I2C_SDAT<='Z';
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121 | if(FPGA_I2C_SDAT='0')then
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122 | fsm_spi<=data_low;
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123 | end if;
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124 | end if;
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125 |
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126 | when data_low=>
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127 | --------------------und jetzt die nächste 8 bit----------
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128 | LEDR(9 downto 6)<="1000";
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129 | if(data_index>0)then
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130 | FPGA_I2C_SDAT<=data_out(data_index);
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131 | data_index<=data_index-1;
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132 | else
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133 | FPGA_I2C_SDAT<=data_out(data_index);
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134 | fsm_spi<=ack3;
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135 | end if;
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136 | when ack3=>
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137 | LEDR(9 downto 6)<="1001";
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138 | FPGA_I2C_SDAT<='Z';
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139 | if(FPGA_I2C_SDAT='0')then
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140 | fsm_spi<= stop;
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141 | end if;
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142 | when sby =>
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143 | LEDR(9 downto 6)<="0001";
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144 | FPGA_I2C_SDAT<='1';
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145 | data_index<=7;--- addr length
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146 | if (SPI_flag='1')then
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147 | fsm_spi<=start;
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148 | end if;
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149 | when start =>
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150 | --------start Bedienung-----------
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151 | LEDR(9 downto 6)<="0010";
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152 | fsm_spi<=send_addr;
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153 | FPGA_I2C_SDAT<='0';
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154 | when stop =>
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155 | --------- stop Bedienung ------------
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156 | LEDR(9 downto 6)<="1010";
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157 | FPGA_I2C_SDAT<='1';
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158 | fsm_spi<=sby;
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159 |
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160 | spi_clk_en<='0';
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161 |
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162 | when others=>NULL;
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163 | end case;
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164 | end if;
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165 | end process;
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166 |
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167 |
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168 |
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169 |
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170 | process(clk_SPI)
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171 | begin
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172 | if rising_edge(clk_SPI) and single_shot='1' then
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173 | single_shot<='0';
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174 | if (KEY(0)='0' ) then ----wake up from stand by
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175 | SPI_flag<='1';
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176 | data_H<="0000110";
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177 | data_L<="001101010";
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178 | elsif (KEY(1)='0' ) then---DSP mode,16 bit, data at 2nd BLCK, slave mode
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179 | SPI_flag<='1';
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180 | data_H<="0000110";
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181 | data_L<="000010011";
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182 | elsif (KEY(2)='0') then---activ control
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183 | SPI_flag<='1';
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184 | data_H<="0001001";
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185 | data_L<="111111111";
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186 | elsif (KEY(3)='0' AND SW(0)='0') then---remove mute
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187 | SPI_flag<='1';
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188 | data_H<="0000000";
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189 | data_L<="100010111";
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190 | elsif (KEY(3)='0' AND SW(0)='1') then---reset
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191 | SPI_flag<='1';
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192 | data_H<="0001111";
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193 | data_L<="000000000";
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194 | end if;
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195 |
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196 | end if;
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197 |
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198 |
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199 | if rising_edge(clk_SPI) and single_shot='0' then
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200 | SPI_flag<='0';
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201 | end if;
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202 |
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203 | if rising_edge(clk_SPI) and KEY="1111" then
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204 | single_shot<='1';
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205 | end if;
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206 | end process;
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207 |
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208 |
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209 | end main;
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