VGA an 50MHZ anpassen, wie geht das?

bernd Gast #4975288
Lesenswert?
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Wie kann man diese VGA-CLK bitte für ein Board mit 50MHZ anpassen?

Danke.

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`default_nettype none      //disable implicit definitions by Verilog

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module top(        //top module and signals wired to FPGA pins

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  CLK100MHz,

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  vga_r,

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  vga_g,

7
  vga_b,

8
  vga_hs,

9
  vga_vs,

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  ps2_clk,

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  ps2_data

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);

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input      CLK100MHz;  // Oscillator input 100Mhz

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output  [2:0]     vga_r;    // VGA Red 3 bit

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output  [2:0]     vga_g;    // VGA Green 3 bit

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output  [2:0]     vga_b;    // VGA Blue 3 bit

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output            vga_hs;    // H-sync pulse 

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output            vga_vs;    // V-sync pulse

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input      ps2_clk;  // PS2 clock

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input      ps2_data;  // PS2 data

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parameter h_pulse   = 96;  //H-SYNC pulse width 96 * 40 ns (25 Mhz) = 3.84 uS

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parameter h_bp      = 48;  //H-BP back porch pulse width

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parameter h_pixels  = 640;  //H-PIX Number of pixels horisontally

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parameter h_fp      = 16;  //H-FP front porch pulse width

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parameter h_pol     = 1'b0;  //H-SYNC polarity

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parameter h_frame   = 800;  //800 = 96 (H-SYNC) + 48 (H-BP) + 640 (H-PIX) + 16 (H-FP)

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parameter v_pulse   = 2;  //V-SYNC pulse width

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parameter v_bp      = 33;  //V-BP back porch pulse width

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parameter v_pixels  = 480;  //V-PIX Number of pixels vertically

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parameter v_fp      = 10;  //V-FP front porch pulse width

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parameter v_pol     = 1'b1;  //V-SYNC polarity

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parameter v_frame   = 525;  // 525 = 2 (V-SYNC) + 33 (V-BP) + 480 (V-PIX) + 10 (V-FP)

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parameter square_size = 10;  //size of the square we will move

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parameter init_x = 320;    //initial square position X

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parameter init_y = 240;    //initial square position Y

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reg  [1:0]    clk_div;  // 2 bit counter

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wire      vga_clk;  

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assign   vga_clk   = clk_div[1];    // 25Mhz clock = 100Mhz divided by 2-bit counter

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always @ (posedge CLK100MHz) begin    // 2-bt counter ++ on each positive edge of 100Mhz clock

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  clk_div <= clk_div + 2'b1;

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end

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reg     [2:0]     vga_r_r;  //VGA color registers R,G,B x 3 bit

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reg     [2:0]     vga_g_r;

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reg     [2:0]     vga_b_r;

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reg               vga_hs_r;  //H-SYNC register

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reg               vga_vs_r;  //V-SYNC register

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assign   vga_r     = vga_r_r;    //assign the output signals for VGA to the VGA registers

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assign   vga_g     = vga_g_r;

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assign   vga_b     = vga_b_r;

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assign   vga_hs     = vga_hs_r;

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assign   vga_vs     = vga_vs_r;

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reg     [7:0]    timer_t = 8'b0;  // 8 bit timer with 0 initialization

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reg               reset = 1;  

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reg     [9:0]     c_row;    //complete frame register row

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reg     [9:0]     c_col;    //complete frame register colum

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reg     [9:0]     c_hor;    //visible frame register horisontally

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reg     [9:0]     c_ver;    //visible  frame register vertically

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reg      disp_en;  //display enable flag

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reg  [9:0]    sq_pos_x;  //position of square center X, Y

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reg  [9:0]    sq_pos_y;

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wire  [9:0]    l_sq_pos_x;  //upper left and down right corners of the square

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wire  [9:0]    r_sq_pos_x;

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wire  [9:0]    u_sq_pos_y;

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wire  [9:0]    d_sq_pos_y;

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assign   l_sq_pos_x   = sq_pos_x - square_size;

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assign   r_sq_pos_x   = sq_pos_x + square_size;

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assign   u_sq_pos_y   = sq_pos_y - square_size;

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assign   d_sq_pos_y   = sq_pos_y + square_size;

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reg  [3:0]    ps2_cntr;    // 4-bit PS2 clock counter

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reg  [7:0]    ps2_data_reg;    // 8-bit PS2 data register

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reg  [7:0]    ps2_data_reg_prev;  // previous 8-bit PS data register

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reg  [7:0]    ps2_data_reg_prev1;  // previous previous 8-bit data register

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reg  [10:0]    ps2_dat_r;    // 11-bit complete PS2 frame register

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reg  [1:0]    ps2_clk_buf;    // PS2 clock buffer

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wire      ps2_clk_pos;    // PS2 positive edge detected signal

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reg      u_arr = 0;    //PS2 arrow keys detect flags

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reg      l_arr = 0;

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reg      d_arr = 0;

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reg      r_arr = 0;

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reg  [20:0]  arr_timer;  // delay between key service

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reg  [19:0]  sq_figure  [0:19];

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wire  [4:0]  sq_fig_x;

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wire  [4:0]  sq_fig_y;

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assign sq_fig_x = c_col - l_sq_pos_x;      // our figure's x axis when in square boundary

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assign sq_fig_y = c_row - u_sq_pos_y;      // our figure's y axis when in square boundary

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assign ps2_clk_pos = (ps2_clk_buf == 2'b01);  // edge detector positive edge is when the buffer is '10'

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always @ (posedge vga_clk) begin        //25Mhz clock

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  if(timer_t > 250) begin          // generate 10 uS RESET signal 

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    reset <= 0;

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  end

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  else begin

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    reset <= 1;          //while in reset display is disabled, suare is set to initial position

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    timer_t <= timer_t + 1;

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    disp_en <= 0;      

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    sq_pos_x <= init_x;        

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    sq_pos_y <= init_y;

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  end

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  if(reset == 1) begin          //while RESET is high init counters

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    sq_figure[0][19:0] <=  20'b00000000000000000000;

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    sq_figure[1][19:0] <=  20'b00000001111100000000;

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    sq_figure[2][19:0] <=  20'b00000111111111000000;

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    sq_figure[3][19:0] <=  20'b00011111111111110000;

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    sq_figure[4][19:0] <=  20'b00111111111111111000;

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    sq_figure[5][19:0] <=  20'b00111111111111111000;

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    sq_figure[6][19:0] <=  20'b01111111111111111100;

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    sq_figure[7][19:0] <=  20'b01111111111111111100;

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    sq_figure[8][19:0] <=  20'b11111111111111111110;

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    sq_figure[9][19:0] <=  20'b11111111111111111110;

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    sq_figure[10][19:0] <=  20'b11111111111111111110;

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    sq_figure[11][19:0] <=  20'b11111111111111111110;

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    sq_figure[12][19:0] <=  20'b11111111111111111110;

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    sq_figure[13][19:0] <=  20'b01111111111111111100;

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    sq_figure[14][19:0] <=  20'b01111111111111111100;

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    sq_figure[15][19:0] <=  20'b00111111111111111000;

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    sq_figure[16][19:0] <=  20'b00111111111111111000;

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    sq_figure[17][19:0] <=  20'b00011111111111110000;

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    sq_figure[18][19:0] <=  20'b00000111111111000000;

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    sq_figure[19][19:0] <=  20'b00000001111100000000;

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    c_hor <= 0;

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    c_ver <= 0;

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    vga_hs_r <= 1;

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    vga_vs_r <= 0;

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    c_row <= 0;

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    c_col <= 0;

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  end

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  else begin            // update current beam position

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    if(c_hor < h_frame - 1) begin

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      c_hor <= c_hor + 1;

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    end

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    else begin

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      c_hor <= 0;

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      if(c_ver < v_frame - 1) begin

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        c_ver <= c_ver + 1;

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      end

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      else begin

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        c_ver <= 0;

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      end

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    end

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  end

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  if(c_hor < h_pixels + h_fp + 1 || c_hor > h_pixels + h_fp + h_pulse) begin  // H-SYNC generator

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    vga_hs_r <= ~h_pol;

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  end

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  else begin

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    vga_hs_r <= h_pol;

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  end

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  if(c_ver < v_pixels + v_fp || c_ver > v_pixels + v_fp + v_pulse) begin    //V-SYNC generator

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    vga_vs_r <= ~v_pol;

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  end

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  else begin

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    vga_vs_r <= v_pol;

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  end

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  if(c_hor < h_pixels) begin    //c_col and c_row counters are updated only in the visible time-frame

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    c_col <= c_hor;

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  end

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  if(c_ver < v_pixels) begin

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    c_row <= c_ver;

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  end

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  if(c_hor < h_pixels && c_ver < v_pixels) begin    //VGA color signals are enabled only in the visible time frame

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    disp_en <= 1;

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  end

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  else begin

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    disp_en <= 0;

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  end

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  if(disp_en == 1 && reset == 0) begin

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    if(c_row == 0 || c_col == 0 || c_row == v_pixels-1 || c_col == h_pixels-1) begin  //generate red frame with size 640x480

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      vga_r_r <= 7;

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      vga_g_r <= 0;

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      vga_b_r <= 0;

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    end

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    else if(c_col > l_sq_pos_x && c_col < r_sq_pos_x && c_row > u_sq_pos_y && c_row < d_sq_pos_y) begin  //generate blue square

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      //vga_r_r <= 7;

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      //vga_g_r <= 0;

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      //vga_b_r <= 7;

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      if(sq_figure[sq_fig_y][sq_fig_x] == 1) begin

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      vga_r_r <= 7;

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      vga_g_r <= 0;

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      vga_b_r <= 7;

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      end

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      else begin

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      vga_r_r <= 0;

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      vga_g_r <= 0;

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      vga_b_r <= 0;

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      end

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    end

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    else begin      //everything else is black

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      vga_r_r <= 0;

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      vga_g_r <= 0;

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      vga_b_r <= 0;

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    end

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  end

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  else begin      //when display is not enabled everything is black

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    vga_r_r <= 0;

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    vga_g_r <= 0;

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    vga_b_r <= 0;

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  end

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  if(c_row == 1 && c_col == 1) begin    //once per video frame

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    if(u_arr) begin

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      if (sq_pos_y > square_size) begin

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        sq_pos_y <= sq_pos_y - 1;

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      end

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      else begin

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        u_arr <= 0;

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        d_arr <= 1;

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      end

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    end;

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    if(d_arr) begin

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      if (sq_pos_y < (v_pixels - 1 - square_size)) begin

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        sq_pos_y <= sq_pos_y + 1;

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      end

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      else begin

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        d_arr <= 0;

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        u_arr <= 1;

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      end

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    end;

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    if(l_arr) begin

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      if (sq_pos_x > square_size) begin

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        sq_pos_x <= sq_pos_x - 1;

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      end

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      else begin

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        l_arr <= 0;

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        r_arr <= 1;

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      end

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    end;

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    if(r_arr) begin

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      if (sq_pos_x < (h_pixels - 1 - square_size)) begin

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        sq_pos_x <= sq_pos_x + 1;

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      end

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      else begin

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        r_arr <= 0;

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        l_arr <= 1;

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      end

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    end;

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  end

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  ps2_clk_buf[1:0] <= {ps2_clk_buf[0], ps2_clk};  // shift old value left and get current value of ps2_clk

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  if(ps2_clk_pos == 1) begin      // on positive edge

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    ps2_cntr <= ps2_cntr + 1;

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    if(ps2_cntr == 10) begin    // when we got 10 clocks save the PS2 data to ps2_data_reg, ps2_data_reg_prev and ps2_data_reg_prev1 

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      ps2_cntr <= 0;      // so we have last 3 data values captured from PS2 keyboard

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      ps2_data_reg[7] <= ps2_dat_r[0];

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      ps2_data_reg[6] <= ps2_dat_r[1];

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      ps2_data_reg[5] <= ps2_dat_r[2];

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      ps2_data_reg[4] <= ps2_dat_r[3];

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      ps2_data_reg[3] <= ps2_dat_r[4];

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      ps2_data_reg[2] <= ps2_dat_r[5];

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      ps2_data_reg[1] <= ps2_dat_r[6];

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      ps2_data_reg[0] <= ps2_dat_r[7];

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      ps2_data_reg_prev <= ps2_data_reg;

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      ps2_data_reg_prev1 <= ps2_data_reg_prev;

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    end

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    ps2_dat_r <= {ps2_dat_r[9:0], ps2_data};  // data shift left

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  end

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/*  if(ps2_data_reg_prev1 == 8'he0 && ps2_data_reg_prev == 8'hf0) begin  // 0xE0 0xF0 sequaence means key released

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    if(ps2_data_reg == 8'h75) begin

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      u_arr <= 0;        //0x75 up key

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    end

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    else if(ps2_data_reg == 8'h6b) begin

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      l_arr <= 0;        //0x6B left key

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    end

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    else if(ps2_data_reg == 8'h72) begin

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      d_arr <= 0;        //0x72 down key

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    end

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    else if(ps2_data_reg == 8'h74) begin

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      r_arr <= 0;        //0x74 right key

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    end

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  end

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*/  

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  arr_timer <= arr_timer + 1;

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  if(arr_timer == 0) begin

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    sq_figure[8][19:0] <=  sq_figure[8][19:0] ^ 20'b00000001111000000000;

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    sq_figure[9][19:0] <=  sq_figure[9][19:0] ^ 20'b00000001111000000000;

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    sq_figure[10][19:0] <=  sq_figure[10][19:0] ^ 20'b00000001111000000000;

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    sq_figure[11][19:0] <=  sq_figure[11][19:0] ^ 20'b00000001111000000000;

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    if(ps2_data_reg_prev == 8'he0) begin      //0xE0  means key pressed

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      if(ps2_data_reg == 8'h75) begin    

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        if(u_arr == 1) begin

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          u_arr <= 1;        //0x75 up key  

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          d_arr <= 0;

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          l_arr <= 0;

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          r_arr <= 0;

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        end

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        else begin

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          u_arr <= 1;        //0x75 up key  

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          d_arr <= 0;

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        end

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        ps2_data_reg <= 0;

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      end

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      if(ps2_data_reg == 8'h6b) begin    

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        if(l_arr == 1) begin

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          l_arr <= 1;        //0x6B left key

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          r_arr <= 0;

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          u_arr <= 0;

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          d_arr <= 0;

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        end

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        else begin

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          l_arr <= 1;        //0x6B left key

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          r_arr <= 0;

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        end

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        ps2_data_reg <= 0;

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      end

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      if(ps2_data_reg == 8'h72) begin

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        if(d_arr == 1) begin

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          d_arr <= 1;        //0x72 down key

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          u_arr <= 0;

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          l_arr <= 0;

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          r_arr <= 0;

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        end

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        else begin

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          d_arr <= 1;        //0x72 down key

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          u_arr <= 0;

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        end

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        ps2_data_reg <= 0;

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      end

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      if(ps2_data_reg == 8'h74) begin

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        if(r_arr == 1) begin

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          r_arr <= 1;        //0x74 right key

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          l_arr <= 0;

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          u_arr <= 0;

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          d_arr <= 0;

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        end

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        else begin

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          r_arr <= 1;        //0x74 right key

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          l_arr <= 0;

362
        end

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        ps2_data_reg <= 0;

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      end

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    end  

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  end

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end

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endmodule
Antwort Zitieren Bearbeiten Thread verschieben Thread sperren Anmeldepflicht aktivieren Anpinnen Thread löschen Thread mit anderem zusammenführen Beitrag melden
Lothar M. Moderator (Firma: Titel) Persönliche Seite #4975306
Lesenswert?
• ▲
▼ 
bernd schrieb:
> Wie kann man diese VGA-CLK bitte für ein Board mit 50MHZ anpassen?
Nimm eine PLL/DLL/DCM und mach aus den 50Mhz die 100MHz, die das Design 
wil...


> Wie kann man diese VGA-CLK bitte für ein Board mit 50MHZ anpassen?
Wo ist der "Taktteiler"?
1
assign   vga_clk   = clk_div[1];    // 25Mhz clock = 100Mhz divided by 2-bit counter

2


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always @ (posedge CLK100MHz) begin    // 2-bt counter ++ on each positive edge of 100Mhz clock

4
  clk_div <= clk_div + 2'b1;

5
end

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7
always @ (posedge vga_clk) begin        //25Mhz clock

8
  ...


BTW:
Das ist ein offensichtlich hingebasteltes, zurechtgemurkstes 
Anfängerdesign, denn per Zähler werden in FPGAs keine Takte erzeugt. Ein 
brauchbares synchrones Design arbeitet mit Clock-Enables. Etwa so:
1
reg  vga_clken;  

2


3
always @ (posedge CLK50MHz) begin    // generate clock enable for 25 MHz

4
  vga_clken <= not vga_clken;

5
end

6


7
always @ (posedge CLK50MHz) begin    // the one and only clock!

8
  if (vga_clken==1) begin            // 25MHz VGA

9
    ...
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