1 | ----------------------------------------------------------------------------
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2 | -- restoring.vhd
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3 | --
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4 | -- Implements a sequential version of restoring division algorithm
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5 | -- section 3.2 Loop-unrolling and digit-serial processing
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6 | -- x = xn-1 xn-2 ... x0: natural
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7 | -- y = yn-1 yn-2 ... y0: natural
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8 | -- condition: x < y
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9 | -- quotient q = 0.q1 ... qp: non-negative fractional
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10 | -- remainder r = rn-1 rn-2 ... r0: natural
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11 | -- x = (0.q1 q2 ... qp)·y + (r/y)·2-p with r < y
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12 | --
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13 | ----------------------------------------------------------------------------
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14 |
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15 | LIBRARY IEEE;
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16 | USE IEEE.STD_LOGIC_1164.ALL;
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17 | USE IEEE.STD_LOGIC_ARITH.ALL;
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18 | USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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19 | ENTITY restoring IS
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20 | GENERIC(n: NATURAL:=8; p: NATURAL:= 6);
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21 | PORT(
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22 | x, y: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
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23 | clk, reset, start:IN STD_LOGIC;
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24 | quotient: OUT STD_LOGIC_VECTOR(1 TO p);
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25 | remainder: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);
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26 | done: OUT STD_LOGIC
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27 | );
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28 | END restoring;
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29 |
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30 | ARCHITECTURE circuit OF restoring IS
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31 | SIGNAL r, next_r: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
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32 | SIGNAL long_y, two_r, dif: STD_LOGIC_VECTOR(n DOWNTO 0);
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33 | SIGNAL load, update: STD_LOGIC;
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34 | SIGNAL q: STD_LOGIC_VECTOR(1 TO p);
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35 |
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36 | SUBTYPE index IS NATURAL RANGE 0 TO p-1;
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37 | SIGNAL count: index;
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38 | TYPE state IS RANGE 0 TO 3;
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39 | SIGNAL current_state: state;
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40 |
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41 | BEGIN
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42 | long_y <= '0'&y;
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43 | two_r <= r&'0';
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44 | dif <= two_r - long_y;
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45 | WITH dif(n) SELECT next_r <= dif(n-1 DOWNTO 0) WHEN '0', two_r(n-1 DOWNTO 0) WHEN OTHERS;
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46 |
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47 | remainder_register: PROCESS(clk)
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48 | BEGIN
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49 | IF clk'EVENT AND clk = '1' THEN
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50 | IF load = '1' THEN r <= x;
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51 | ELSIF update = '1' THEN r <= next_r;
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52 | END IF;
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53 | END IF;
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54 | END PROCESS;
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55 | remainder <= r;
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56 |
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57 | quotient_register: PROCESS(clk)
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58 | BEGIN
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59 | IF clk'EVENT AND clk = '1' THEN
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60 | IF load = '1' THEN q <= (others => '0');
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61 | ELSIF update = '1' THEN q <= q(2 TO p)&NOT(dif(n));
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62 | END IF;
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63 | END IF;
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64 | END PROCESS;
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65 | quotient <= q;
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66 |
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67 | counter: PROCESS(clk)
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68 | BEGIN
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69 | IF clk'EVENT and clk = '1' THEN
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70 | IF load = '1' THEN count <= 0;
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71 | ELSIF update = '1' THEN count <= (count+1) MOD p;
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72 | END IF;
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73 | END IF;
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74 | END PROCESS;
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75 |
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76 | next_state: PROCESS(clk)
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77 | BEGIN
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78 | IF reset = '1' THEN current_state <= 0;
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79 | ELSIF clk'EVENT AND clk = '1' THEN
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80 | CASE current_state IS
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81 | WHEN 0 => IF start = '0' THEN current_state <= 1; END IF;
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82 | WHEN 1 => IF start = '1' THEN current_state <= 2; END IF;
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83 | WHEN 2 => current_state <= 3;
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84 | WHEN 3 => IF count = p-1 THEN current_state <= 0; END IF;
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85 | END CASE;
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86 | END IF;
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87 | END PROCESS;
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88 |
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89 | output_function: PROCESS(clk, current_state)
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90 | BEGIN
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91 | CASE current_state IS
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92 | WHEN 0 TO 1 => load <= '0'; update <= '0'; done <= '1';
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93 | WHEN 2 => load <= '1'; update <= '0'; done <= '0';
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94 | WHEN 3 => load <= '0'; update <= '1'; done <= '0';
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95 | END CASE;
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96 | END PROCESS;
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97 |
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98 | END circuit;
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