1 | /**
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2 | * Name: USI TWI Slave driver - I2C/TWI-EEPROM
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3 | * Version: 1.3 - Stable
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4 | * Autor: Martin Junghans jtronics@gmx.de
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5 | * Page: www.jtronics.de
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6 | * License: GNU General Public License
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7 | *
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8 | * Update: 09.09.2011 - ATtiny24, ATtiny44, ATtiny88
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9 | *
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10 | * Created from Atmel source files for Application Note AVR312:
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11 | * Using the USI Module as an I2C slave like an I2C-EEPROM.
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12 | * 02.02.2013 - reworked by Willi Thiel
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13 | */
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14 |
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15 | #include <avr/io.h>
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16 | #include <avr/interrupt.h>
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17 | #include "i2cslave.h"
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18 |
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19 | #define SET_USI_TO_SEND_ACK( ) { USIDR = 0; \
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20 | DDR_USI |= ( 1 << PORT_USI_SDA ); \
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21 | USISR = ( 0 << USI_START_COND_INT ) | \
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22 | ( 1 << USIOIF ) | ( 1 << USIPF ) | \
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23 | ( 1 << USIDC )| \
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24 | ( 0x0E << USICNT0 );} /*!< Prepare ACK; Set SDA as output; Clear all interrupt flags, except Start Cond; Set USI counter to shift 1 bit */
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25 |
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26 | #define SET_USI_TO_READ_ACK( ) { USIDR = 0; \
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27 | DDR_USI &= ~( 1 << PORT_USI_SDA ); \
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28 | USISR = ( 0 << USI_START_COND_INT ) | \
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29 | ( 1 << USIOIF) | \
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30 | ( 1 << USIPF ) | \
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31 | ( 1 << USIDC ) | \
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32 | ( 0x0E << USICNT0 );} /*!< Set SDA as input; Prepare ACK; Clear all interrupt flags, except Start Cond; Set USI counter to shift 1 bit */
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33 |
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34 | #define SET_USI_TO_TWI_START_CONDITION_MODE( ) { \
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35 | USICR = ( 1 << USISIE ) | ( 0 << USIOIE ) | \
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36 | ( 1 << USIWM1 ) | ( 0 << USIWM0 ) | \
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37 | ( 1 << USICS1 ) | ( 0 << USICS0 ) | ( 0 << USICLK ) | \
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38 | ( 0 << USITC ); \
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39 | USISR = ( 0 << USI_START_COND_INT ) | ( 1 << USIOIF ) | ( 1 << USIPF ) | \
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40 | ( 1 << USIDC ) | ( 0x0 << USICNT0 ); } /*!< Enable Start Condition Interrupt, disable Overflow Interrupt; Set USI in Two-wire mode, no USI Counter overflow hold; Shift Register Clock Source = External, positive edge; 4-Bit Counter Source = external, both edges; No toggle clock-port pin; Clear all interrupt flags, except Start Cond */
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41 |
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42 | #define SET_USI_TO_SEND_DATA( ) { DDR_USI |= ( 1 << PORT_USI_SDA ); \
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43 | USISR = ( 0 << USI_START_COND_INT ) | ( 1 << USIOIF ) | ( 1 << USIPF ) | \
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44 | ( 1 << USIDC) | \
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45 | ( 0x0 << USICNT0 ); \
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46 | } /*!< Set SDA as output; Clear all interrupt flags, except Start Cond; Set USI to shift out 8 bits */
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47 |
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48 | #define SET_USI_TO_READ_DATA( ) { DDR_USI &= ~( 1 << PORT_USI_SDA ); \
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49 | USISR = ( 0 << USI_START_COND_INT ) | ( 1 << USIOIF ) | \
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50 | ( 1 << USIPF ) | ( 1 << USIDC ) | \
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51 | ( 0x0 << USICNT0 ); \
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52 | } /*!< Set SDA as input; Clear all interrupt flags, except Start Cond; Set USI to shift out 8 bits */
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53 |
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54 | typedef enum {
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55 | USI_SLAVE_CHECK_ADDRESS = 0x00, USI_SLAVE_SEND_DATA = 0x01, USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA = 0x02, USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA = 0x03, USI_SLAVE_REQUEST_DATA = 0x04, USI_SLAVE_GET_DATA_AND_SEND_ACK = 0x05
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56 | } overflow_state_t;
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57 |
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58 | volatile uint8_t slave_address; /*!< Address of the I2C slave */
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59 | volatile overflow_state_t overflow_state; /*!< overflow state of the I2C slave */
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60 |
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61 | /**
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62 | * Initialize slave
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63 | *
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64 | * @param address The address of the I2C slave device
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65 | */
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66 | void i2c_init(uint8_t address) {
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67 | slave_address = address;
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68 |
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69 | // In Two Wire mode (USIWM1, USIWM0 = 1X), the slave USI will pull SCL
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70 | // low when a start condition is detected or a counter overflow (only
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71 | // for USIWM1, USIWM0 = 11). This inserts a wait state. SCL is released
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72 | // by the ISRs (USI_START_vect and USI_OVERFLOW_vect).
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73 |
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74 | // Set SCL and SDA as output
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75 | DDR_USI |= (1 << PORT_USI_SCL) | (1 << PORT_USI_SDA);
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76 |
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77 | // Set SCL high
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78 | PORT_USI |= (1 << PORT_USI_SCL);
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79 |
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80 | // Set SDA high
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81 | PORT_USI |= (1 << PORT_USI_SDA);
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82 |
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83 | // Set SDA as input
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84 | DDR_USI &= ~(1 << PORT_USI_SDA);
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85 |
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86 | USICR = (1 << USISIE) | // Enable Start Condition Interrupt
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87 | (0 << USIOIE) | // Disable Overflow Interrupt
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88 | (1 << USIWM1) | (0 << USIWM0) | // Set USI in Two-wire mode, no USI Counter overflow hold
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89 | (1 << USICS1) | (0 << USICS0) | (0 << USICLK) | // Shift Register Clock Source = external, positive edge 4-Bit Counter Source = external, both edges
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90 | (0 << USITC); // No toggle clock-port pin
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91 |
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92 | // clear all interrupt flags and reset overflow counter
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93 | USISR = (1 << USI_START_COND_INT) | (1 << USIOIF) | (1 << USIPF) | (1 << USIDC);
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94 | }
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95 |
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96 | /**
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97 | * USI Start Condition ISR
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98 | */
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99 | ISR( USI_START_VECTOR) {
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100 |
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101 | // Set default starting conditions for new TWI package
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102 | overflow_state = USI_SLAVE_CHECK_ADDRESS;
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103 |
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104 | // Set SDA as input
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105 | DDR_USI &= ~(1 << PORT_USI_SDA);
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106 |
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107 | // Wait for SCL to go low to ensure the Start Condition has completed (the
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108 | // Start detector will hold SCL low ) - if a Stop Condition arises then leave
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109 | // The interrupt to prevent waiting forever - don't use USISR to test for Stop
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110 | // Condition as in Application Note AVR312 because the Stop Condition Flag is
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111 | // going to be set from the last TWI sequence
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112 |
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113 | while ((PIN_USI & (1 << PIN_USI_SCL)) && !((PIN_USI & (1 << PIN_USI_SDA))))
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114 | ; // SCL his high and SDA is low
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115 |
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116 | // A Stop Condition did not occur
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117 | if (!(PIN_USI & (1 << PIN_USI_SDA))) {
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118 | USICR = (1 << USISIE) | // Keep Start Condition Interrupt enabled to detect RESTART
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119 | (1 << USIOIE) | // Enable Overflow Interrupt
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120 | (1 << USIWM1) | (1 << USIWM0) | // Set USI in Two-wire mode, hold SCL low on USI Counter overflow
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121 | (1 << USICS1) | (0 << USICS0) | (0 << USICLK) | // 4-Bit Counter Source = external, both edges; Clock Source = External, positive edge
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122 | (0 << USITC); // No toggle clock-port pin
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123 |
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124 | } else {
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125 | // A Stop Condition did occur
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126 | USICR = (1 << USISIE) | // Enable Start Condition Interrupt
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127 | (0 << USIOIE) | // Disable Overflow Interrupt
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128 | (1 << USIWM1) | (0 << USIWM0) | // Set USI in Two-wire mode, no USI Counter overflow hold
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129 | (1 << USICS1) | (0 << USICS0) | (0 << USICLK) | // 4-Bit Counter Source = external, both edges; Clock Source = external, positive edge
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130 | (0 << USITC); // No toggle clock-port pin
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131 | }
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132 |
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133 | USISR = (1 << USI_START_COND_INT) | (1 << USIOIF) | // Clear interrupt flags - resetting the Start Condition Flag will release SCL
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134 | (1 << USIPF) | (1 << USIDC) | (0x0 << USICNT0); // Set USI to sample 8 bits (count 16 external SCL pin toggles)
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135 | }
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136 |
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137 | /**
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138 | * ISR( USI_OVERFLOW_VECTOR )
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139 | *
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140 | * Handles all the communication. Only disabled when waiting for a new Start Condition.
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141 | */
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142 | ISR( USI_OVERFLOW_VECTOR) {
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143 | uint8_t data = 0;
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144 | switch (overflow_state) {
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145 |
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146 | /**
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147 | * Address mode: check address and send ACK (and next USI_SLAVE_SEND_DATA) if OK, else reset USI
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148 | */
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149 | case USI_SLAVE_CHECK_ADDRESS:
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150 | // If address is either 0 or own address
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151 | if (USIDR == 0 || (USIDR & ~1) == slave_address) {
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152 | if (USIDR & 0x01) {
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153 | // Master Write Data Mode - Slave transmit
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154 | overflow_state = USI_SLAVE_SEND_DATA;
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155 | } else {
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156 | // Master Read Data Mode - Slave receive
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157 | overflow_state = USI_SLAVE_REQUEST_DATA;
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158 | // Buffer position undefined
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159 | buffer_adr = 0xFF;
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160 | } // end if
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161 | SET_USI_TO_SEND_ACK()
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162 | } else {
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163 | SET_USI_TO_TWI_START_CONDITION_MODE()
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164 | }
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165 | break;
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166 |
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167 | /**
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168 | * Master Write Data Mode - Slave transmit
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169 | */
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170 | // Check reply and goto USI_SLAVE_SEND_DATA if OK, else reset USI
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171 | case USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA:
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172 | if (USIDR) {
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173 | // If NACK, the master does not want more data
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174 | SET_USI_TO_TWI_START_CONDITION_MODE()
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175 | return;
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176 | }
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177 |
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178 | // From here we just drop straight into USI_SLAVE_SEND_DATA if the master sent an ACK
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179 | case USI_SLAVE_SEND_DATA:
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180 | // No buffer position given, set buffer address to 0
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181 | if (buffer_adr == 0xFF) {
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182 | buffer_adr = 0;
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183 | }
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184 |
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185 | // Send data byte
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186 | USIDR = i2c_buffer[buffer_adr];
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187 |
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188 | // Increment buffer address for next byte
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189 | buffer_adr++;
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190 |
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191 | overflow_state = USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA;
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192 | SET_USI_TO_SEND_DATA()
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193 | break;
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194 |
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195 | // Set USI to sample reply from master
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196 | // Next USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA
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197 | case USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA:
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198 | overflow_state = USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA;
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199 | SET_USI_TO_READ_ACK()
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200 | break;
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201 |
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202 | /**
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203 | * Master Read Data Mode - Slave receive
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204 | */
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205 | // Set USI to sample data from master,
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206 | // Next USI_SLAVE_GET_DATA_AND_SEND_ACK
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207 | case USI_SLAVE_REQUEST_DATA:
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208 | overflow_state = USI_SLAVE_GET_DATA_AND_SEND_ACK;
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209 | SET_USI_TO_READ_DATA( )
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210 | break;
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211 |
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212 | // Copy data from USIDR and send ACK
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213 | // Next USI_SLAVE_REQUEST_DATA
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214 | case USI_SLAVE_GET_DATA_AND_SEND_ACK:
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215 | // Read data received
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216 | data = USIDR;
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217 |
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218 | // First access, read buffer position
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219 | if (buffer_adr == 0xFF) {
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220 | // Check if address within buffer size
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221 | if (data <= buffer_size) {
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222 | // Set position as received
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223 | buffer_adr = data;
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224 | } else {
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225 | // Set address to 0
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226 | buffer_adr = 0;
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227 | }
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228 | } else {
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229 | // Ongoing access, receive data
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230 |
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231 | // Write data to buffer
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232 | i2c_buffer[buffer_adr] = data;
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233 |
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234 | // Increment buffer address for next write access
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235 | buffer_adr++;
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236 | }
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237 | // Next USI_SLAVE_REQUEST_DATA
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238 | overflow_state = USI_SLAVE_REQUEST_DATA;
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239 | SET_USI_TO_SEND_ACK( )
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240 | break;
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241 | } // end switch
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242 | } // end ISR( USI_OVERFLOW_VECTOR )
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