Forum: FPGA, VHDL & Co. Implement a FPGA design using a 325 MHz clock


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von Jeeen L. (jeeen_l)


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I'm currently trying to implement a FPGA design using a 325 MHz clock, 
which writes to the SDRAM Controller of a Cyclone V 
5CSEBA6U23I7(http://www.kynix.com/Parts/36331/5CSEBA6U23I7N.html) (Speed 
Grade 7).
When running my IP Core with 2 MHz everything works fine, but when I 
change the PLL clock to either 200 MHz or 325 MHz the data I can observe 
with SignalTap becomes completly random.
I've attached an image, in which I want to point out the 4th signal 
(bRun), which should be constant at 1, but in the observation toggles to 
0 and back to 1. Some other signals also experience completly random 
behaviour, like some internal busses, which carry non-zero data, when 
they should be zero.
I don't think this is an EMC problem, because I'm using a development 
board (DE10-Nano from terasic) and all signals are FPGA-internal, which 
should be able to handle these clockspeeds.

(See attachment ywkni.png)

The IP-Core is written in Verilog and I made sure to synchronize read 
and write operations on different edges of the respective clock to make 
sure, that the signals are stable and not transitioning when being read.
Following you can find the code for my RAM-write state machine, but as 
stated it works perfectly fine at 2 MHz.
If you guys have any idea about the reason for this behaviour I'd be 
very thankful.
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                    imgSize <= imgSize;
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                    nCntCurPos <= 4'b0;
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                    nOutWord <= 256'b0;
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                    fifo_read <= 0;
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                    avm_m0_address <= 27'b0;
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                    avm_m0_writedata <= 256'b0;
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                    avm_m0_write <= 0;
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                    avm_m0_byteenable <= 32'b0;
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                    irqFromFPGAMaster <= state[2];
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                    if(state[2]==0)     state <= 3'b000;
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                    else                    state <= state;
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                end
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            endcase
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        end
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        else//Running, but IRQ hasn't been handled yet, preserve some data
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        begin
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            imgSize <= imgSize;
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            irqFromFPGAMaster <= irqFromFPGAMaster;
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            //irqFromFPGAMaster <= 0;
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            //imgSize <= 32'd0;
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            nCntCurPos <= 4'b0;
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            nOutWord <= 256'b0;
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            state <= 3'b0;
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            fifo_read <= 0;
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            avm_m0_address <= 27'b0;
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            avm_m0_writedata <= 256'b0;
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            avm_m0_write <= 0;
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            avm_m0_byteenable <= 32'b0;
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        end
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    end
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end

Also just fyi: The bRun Signal is being assigned by an Avalon MM-Slave 
connected to the ARm-Processor of the Cyclone V. During the observed 
period there hasn't been any communication with the processor so bRun 
shouldn't change. This also wouldn't explain the NRZ bus, which should 
be RZ, as seen in the Verilog code.

von Lothar M. (Firma: Titel) (lkmiller) (Moderator) Benutzerseite


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Jeeen L. schrieb:
> When running my IP Core with 2 MHz everything works fine, but when I
> change the PLL clock to either 200 MHz or 325 MHz the data I can observe
> with SignalTap becomes completly random.
Did you tell the toolchain about the desired target frequency?
Spoken technically: do you use proper timing constraints?

von Duke Scarring (Gast)


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The schematic list IS43TR16256A-15HBL as memory chip.
Datasheet: http://www.issi.com/WW/pdf/43-46TR16256A-85120AL.pdf

Which chip is really on board?
The IS43tr16256A-15HBL is specified for 1333MT/s. This mean a 
theoretical IO clk with 666 MHz. The real maximum memory clock is 166 
MHz.

https://en.wikipedia.org/wiki/DDR3_SDRAM#JEDEC_standard_modules

Can you explain why you use 325 MHz?

Duke

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