1 | static void SystemClock_Config(void)
|
2 | {
|
3 | RCC_PLLCFGR |= 0x22403208;
|
4 | //RCC_PLLCFGR |= 0010 0010 0100 0000 0011 0010 0000 1000;
|
5 | //Bit 31 0 Reserved
|
6 | //Bit 30:28 010 PLLR Division Factor = 2
|
7 | //Bit 27:24 0010 PLLQ Division Factor = 2
|
8 | //Bit 23 0 Reserved
|
9 | //Bit 22 1 HSE oscillator clock selected as PLL and PLLI2S clock entry
|
10 | //Bit 21:18 0000 Reserved
|
11 | //Bit 17:16 00 PLLP Division Factor = 2
|
12 | //Bit 15 0 Reserved
|
13 | //Bit 14:6 011001000 PLL PLLN Multiplication Faktor = 200
|
14 | //Bit 5:0 001000 PLL PLLM Division Factor = 8
|
15 |
|
16 | RCC_CFGR |= 0x36481012;
|
17 | //RCC_CFGR |= 0011 0110 0100 1000 0001 0000 0001 0010;
|
18 | //Bit 31:30 00 MCO2 System Clock selected
|
19 | //Bit 29:27 110 MCO2 Prescaler = 4
|
20 | //Bit 26:24 110 MCO1 Prescaler = 4
|
21 | //Bit 23 0 Reserved
|
22 | //Bit 22:21 10 MCO1 HSE Oszilator Clock selcted
|
23 | //Bit 20:16 01000 HSE division for RTC Clock = 8
|
24 | //Bit 15:13 000 APB2 Prescaler = 1
|
25 | //Bit 12:10 100 APB1 Prescaler = 2
|
26 | //Bit 9:8 00 Reserved
|
27 | //Bit 7:4 0001 AHB Prescaler = 1
|
28 | //Bit 3:2 00 System clock switch status (set an cleared by hardware)
|
29 | //Bit 1:0 10 PLL selected as system clock
|
30 |
|
31 | RCC_PLLI2SCFGR |= 0x22003010;
|
32 | //RCC_PLLI2SCFGR |= 0010 0010 0000 0000 0011 0000 0001 0000;
|
33 | //Bit 0:5 010000 PLLI2SM Division factor for the main PLL input clock = 16
|
34 | //Bit 14:6 011000000 PLLI2SN Multiplication factor = 192
|
35 | //Bit 21:15 0000000 Reserved
|
36 | //Bit 22 0 PLLI2S entry clock source HSE or HSI (depending on PLLSRC of PLLCFGR)
|
37 | //Bit 23 0 Reserved
|
38 | //Bit 27:24 0010 PLLI2SQ = 2
|
39 | //Bit 30:28 010 PLLI2SR = 2
|
40 | //Bit 31 0 Reserved
|
41 |
|
42 | RCC_CR |= 0x05090000;
|
43 | //RCC_CR |= 0000 0101 0000 1001 0000 0000 0000 0000;
|
44 | //Bit 31:28 0000 Reserved
|
45 | //Bit 26 01 PLLI2SON = 1 enable
|
46 | //Bit 25 0 PLLReady (set by hardware)
|
47 | //Bit 24 1 PLLON Main PLL enable = 1
|
48 | //Bit 23:20 0000 Reserved
|
49 | //Bit 19 1 CSSON clock security system = 1 (enable)
|
50 | //Bit 18 0 HSEBYP HSE clock Bypas = 0 (HSE oscillator not bypassed)
|
51 | //Bit 17 0 HSERDY HSE clock ready flag. Set by hardware to indicate that the HSE oscillator ist stable
|
52 | //Bit 16 1 HSEON HSE clock enable = 1 (HSE oscillator on)
|
53 | //Bit 15:8 00000000 Internal high speed clock calibration
|
54 | //Bit 7:3 00000 Internal high speed clock trimming
|
55 | //Bit 2 0 Reserved
|
56 | //Bit 1 0 HSIRDY set by hardware (0=HSI not ready ; 1=HSI Ready)
|
57 | //Bit 0 0 HSION Set by hardware in case of failure of HSE oscilator etc....}
|