multi-cycle path

module SecondOrderSigmaDeltaDac1v01

 (input            clk ,

  input            clkEna ,

  input  [MSBI:0]  DACin ,  

  output reg       DACout

  );

parameter MSBI=7 ;

reg signed [MSBI:0] din ;

reg signed [MSBI+3:0] del1 ;

reg signed [MSBI+3:0] del2 ;

reg signed [MSBI+3:0] d_q ;

always @(posedge clk) begin

  if ( clkEna ) begin

    din <= DACin ;

    del1 <= din - d_q + del1 ;

    del2 <= din - d_q + del1 - d_q + del2 ;

    if ( din - d_q + del1 - d_q + del2 > 0 )

      begin

      d_q  <= 11'h 100 ;

      DACout <= 1;

      end

     else

      begin

      d_q  <=  11'h 700 ;

      DACout <= 0;

      end

    end

  end   

endmodule