Hallo,
habe mal eine Frage zu meinem Design.
Ich habe in einem Virtex 5 eine Camera Link Full Configuration Output
Schnittstelle implementiert.
Die Daten laufen mit 350MHz, die Sync Clock dazu durch 7, also 50MHz.
Nun will ich dass die Signale im FPGA mit dem selben (!) delay zum Pad
gelangen.
Im Report steht folgendes:
1 | Clock CLK to Pad
|
2 | ---------------+------------+-----------------------+--------+
|
3 | | clk (edge) | | Clock |
|
4 | Destination | to PAD |Internal Clock(s) | Phase |
|
5 | ---------------+------------+-----------------------+--------+
|
6 | ELLISA_CLK_X<0>| 10.980(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
7 | ELLISA_CLK_X<1>| 10.980(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
8 | ELLISA_CLK_Y<0>| 11.148(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
9 | ELLISA_CLK_Y<1>| 11.148(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
10 | ELLISA_CLK_Z<0>| 11.235(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
11 | ELLISA_CLK_Z<1>| 11.235(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
12 | ELLISA_X0<0> | 13.938(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
13 | ELLISA_X0<1> | 13.938(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
14 | ELLISA_X1<0> | 14.037(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
15 | ELLISA_X1<1> | 14.037(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
16 | ELLISA_X2<0> | 14.039(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
17 | ELLISA_X2<1> | 14.039(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
18 | ELLISA_X3<0> | 14.021(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
19 | ELLISA_X3<1> | 14.021(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
20 | ELLISA_Y0<0> | 13.626(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
21 | ELLISA_Y0<1> | 13.626(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
22 | ELLISA_Y1<0> | 14.431(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
23 | ELLISA_Y1<1> | 14.431(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
24 | ELLISA_Y2<0> | 13.877(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
25 | ELLISA_Y2<1> | 13.877(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
26 | ELLISA_Y3<0> | 13.985(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
27 | ELLISA_Y3<1> | 13.985(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
28 | ELLISA_Z0<0> | 13.476(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
29 | ELLISA_Z0<1> | 13.476(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
30 | ELLISA_Z1<0> | 13.646(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
31 | ELLISA_Z1<1> | 13.646(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
32 | ELLISA_Z3<0> | 13.809(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
33 | ELLISA_Z3<1> | 13.809(R)|i_CLKx7_MICROBOLOMETER1| 0.000|
|
34 | ---------------+------------+-----------------------+--------+
|
CLK ist die SystemClock bzw. der Eingangstakt 100MHz
i_CLKx7_MICROBOLOMETER1 = 350MHz (Interner Takt erzeugt aus einer PLL)
ELLISA_CLK_* = 350/7 = 50MHz (synchron im Design erzeugt)
1 | -- __ __ __ __ __ __ __ __ __ __
|
2 | -- CLK __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__...
|
3 | --
|
4 | -- COUNT 0 1 2 3 4 5 6 0 1 2 ...
|
5 | -- __|___________ ___________|___________
|
6 | -- i_CLKx1 |_________________| |_____...
|
7 | CLKx1_GEN: PROCESS(CLK)
|
8 | BEGIN
|
9 | IF CLK = '1' AND CLK'EVENT THEN
|
10 | i_CLKx1 <= '1';
|
11 | IF COUNT < 1 THEN
|
12 | COUNT <= COUNT + 1;
|
13 | ELSIF COUNT >= 1 AND COUNT < 4 THEN
|
14 | i_CLKx1 <= '0';
|
15 | COUNT <= COUNT + 1;
|
16 | ELSIF COUNT >= 4 AND COUNT <= 6 THEN
|
17 | COUNT <= COUNT + 1;
|
18 | IF COUNT = 6 THEN
|
19 | COUNT <= 0;
|
20 | END IF;
|
21 | END IF;
|
22 | END IF;
|
23 | END PROCESS CLKx1_GEN;
|
X*/Y*/Z* Serielle Datenstrom im 350MHz Takt
Der Output der Signale erfolgt über OBUFDS Primitive, z.B.:
1 | ...
|
2 | CLK_Z_OBUFDS: OBUFDS
|
3 | PORT MAP (
|
4 | O => CLK_Z(0), -- Diff_p output (connect directly to top-level port)
|
5 | OB => CLK_Z(1), -- Diff_n output (connect directly to top-level port)
|
6 | I => i_CLKx1 -- Buffer input
|
7 | );
|
8 | ...
|
9 | Y3_OBUFDS: OBUFDS -- Y3 diff I/O
|
10 | PORT MAP (
|
11 | O => Y3(0), -- Diff_p output (connect directly to top-level port)
|
12 | OB => Y3(1), -- Diff_n output (connect directly to top-level port)
|
13 | I => i_Y3 -- Buffer input
|
14 | );
|
15 | ...
|
Die Frage ist, wie bekomme ich die clk (edge) to PAD Zeiten auf das
gleiche Delay (min. < 1ns)?
Welche Constraints könnte ich da anwenden? OFFSET OUT? Wie am besten?
Als alternative zu meinem aktuellen Design hätte ich auch OSERDES
Primitive benutzen können. Werden da die clk to PAD delay automatisch
vom OSERDES geregelt?
Hoffe ihr könnt mir helfen
LG