dsub(vga) Monitor out of range

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity vga is

    Port ( clk50 : in  STD_LOGIC;

           vga_red : out  STD_LOGIC_VECTOR (2 downto 0);

           vga_green : out  STD_LOGIC_VECTOR (2 downto 0);

           vga_blue : out  STD_LOGIC_VECTOR (2 downto 1);

           vga_hsync : out  STD_LOGIC;

           vga_vsync : out  STD_LOGIC;

           frame_addr : out  STD_LOGIC_VECTOR (14 downto 0);

           frame_pixel : in  STD_LOGIC_VECTOR (7 downto 0));

end vga;

architecture Behavioral of vga is

   -- Timing constants

   constant hRez       : natural := 640;

   constant vRez       : natural := 480;

   constant hMaxCount  : natural := 799;

   constant hStartSync : natural := 655;

   constant hEndSync   : natural := 751;

   constant vMaxCount  : natural := 525;

   constant vStartSync : natural := 490;

   constant vEndSync   : natural := 491;

   constant hsync_active : std_logic := '1';

   constant vsync_active : std_logic := '1';

   signal hCounter : unsigned(10 downto 0) := (others => '0');

   signal vCounter : unsigned(9 downto 0) := (others => '0');

   signal address : unsigned(16 downto 0) := (others => '0');

   signal blank : std_logic := '1';

  SIGNAL clk25  :STD_LOGIC;

begin

   frame_addr <= std_logic_vector(address(16 downto 2));

  process (clk50)

begin

  if clk50'event and clk50='1' then

    if (clk25 = '0')then

      clk25 <= '1';

    else

      clk25 <= '0';

    end if;

  end if;

end process;  

   process(clk25)

   begin

      if rising_edge(clk25) then

         -- Count the lines and rows      

         if hCounter = hMaxCount-1 then

            hCounter <= (others => '0');

            if vCounter = vMaxCount-1 then

               vCounter <= (others => '0');

            else

               vCounter <= vCounter+1;

            end if;

         else

            hCounter <= hCounter+1;

         end if;

         if blank = '0' then

            vga_red   <= frame_pixel(7 downto 5);

            vga_green <= frame_pixel(4 downto 2);

            vga_blue  <= frame_pixel(1 downto 0);

         else

            vga_red   <= (others => '0');

            vga_green <= (others => '0');

            vga_blue  <= (others => '0');

         end if;

         if vCounter  >= vRez then

            address <= (others => '0');

            blank <= '1';

         else 

            if hCounter  >= 0 and hCounter  < 640 then

               blank <= '0';

               address <= address+1;

            else

               blank <= '1';

            end if;

         end if;

         if hCounter > hStartSync and hCounter <= hEndSync then

            vga_hSync <= hsync_active;

         else

            vga_hSync <= not hsync_active;

         end if;

         if vCounter >= vStartSync and vCounter <= vEndSync then

            vga_vSync <= vsync_active;

         else

            vga_vSync <= not vsync_active;

         end if;

      end if;

   end process;

end Behavioral;

----------------------------------------------------------------------------------

-- Company: 

-- Engineer: 

-- 

-- Create Date:    00:47:27 09/09/2019 

-- Design Name: 

-- Module Name:    frame_buffer - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity frame_buffer is

  generic(

    ADDR_WIDTH: integer := 15;

    DATA_WIDTH: integer := 8

    );

    Port ( clka : in  STD_LOGIC;

           wea : in  STD_LOGIC;

           addra : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);

           dina : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);

           clkb : in  STD_LOGIC;

           addrb : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);

           doutb : out  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0));

end frame_buffer;

architecture Behavioral of frame_buffer is

  type ram_type is array (2**ADDR_WIDTH-1 downto 0)

    of STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);

  signal ram: ram_type;

  signal addr_b_reg: STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);

  SIGNAL clk25  :STD_LOGIC;

begin

  process (clkb)

     begin

    if clkb'event and clkb='1' then

          if (clk25 = '0')then

             clk25 <= '1';

          else

             clk25 <= '0';

          end if;

       end if;

     end process;

  process(clka)

  begin

    if(clka'event and clka = '1') then

      if(wea = '1') then

        ram(to_integer(unsigned(addra))) <= dina;

      end if;

      addr_b_reg <= addrb;

    end if;

  end process;

  process(clk25)

  begin

    doutb <= ram(to_integer(unsigned(addr_b_reg)));

  end process;

end Behavioral;