1 | void main(void) |
2 | {
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3 | |
4 | // Port D initialization
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5 | // Function: Bit7=Out Bit6=Out Bit5=In Bit4=In Bit3=In Bit2=In Bit1=In Bit0=In
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6 | DDRD=(1<<DDD7) | (1<<DDD6) | (0<<DDD5) | (0<<DDD4) | (0<<DDD3) | (0<<DDD2) | (0<<DDD1) | (0<<DDD0); |
7 | // State: Bit7=0 Bit6=0 Bit5=T Bit4=T Bit3=T Bit2=T Bit1=T Bit0=T
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8 | PORTD=(0<<PORTD7) | (0<<PORTD6) | (0<<PORTD5) | (0<<PORTD4) | (0<<PORTD3) | (0<<PORTD2) | (0<<PORTD1) | (0<<PORTD0); |
9 | |
10 | // Timer/Counter 2 initialization
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11 | // Clock source: System Clock
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12 | // Clock value: 125,000 kHz
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13 | // Mode: Fast PWM top=0xFF
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14 | // OC2A output: Non-Inverted PWM
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15 | // OC2B output: Non-Inverted PWM
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16 | // Timer Period: 2,048 ms
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17 | // Output Pulse(s):
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18 | // OC2A Period: 2,048 ms Width: 0,77101 ms
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19 | // OC2B Period: 2,048 ms Width: 1,028 ms
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20 | ASSR=(0<<EXCLK) | (0<<AS2); |
21 | TCCR2A=(1<<COM2A1) | (0<<COM2A0) | (1<<COM2B1) | (0<<COM2B0) | (1<<WGM21) | (1<<WGM20); |
22 | TCCR2B=(0<<WGM22) | (1<<CS22) | (0<<CS21) | (0<<CS20); |
23 | TCNT2=0x00; |
24 | OCR2A=0x60; |
25 | OCR2B=0x80; |
26 | |
27 | // USART2 initialization
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28 | // Communication Parameters: 8 Data, 1 Stop, No Parity
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29 | // USART2 Receiver: On
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30 | // USART2 Transmitter: On
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31 | // USART2 Mode: Asynchronous
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32 | // USART2 Baud Rate: 9600
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33 | UCSR2A=(0<<RXC2) | (0<<TXC2) | (0<<UDRE2) | (0<<FE2) | (0<<DOR2) | (0<<UPE2) | (0<<U2X2) | (0<<MPCM2); |
34 | UCSR2B=(0<<RXCIE2) | (0<<TXCIE2) | (0<<UDRIE2) | (1<<RXEN2) | (1<<TXEN2) | (0<<UCSZ22) | (0<<RXB82) | (0<<TXB82); |
35 | UCSR2C=(0<<UMSEL21) | (0<<UMSEL20) | (0<<UPM21) | (0<<UPM20) | (0<<USBS2) | (1<<UCSZ21) | (1<<UCSZ20) | (0<<UCPOL2); |
36 | UBRR2H=0x00; |
37 | UBRR2L=0x33; |
38 | |
39 | // Ensure that the USART2 is enabled
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40 | PRR2&= ~(1<<PRUSART2); |
41 | |
42 | while (1) |
43 | {
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44 | }
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45 | }
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Sobald RXEN2 und/oder TXEN2 gesetzt werden, ist OC2A tot. OC2B läuft weiter, UART funktioniert auch. Das einzige, was mir sinnvoll erscheint ist das XCK2-bit, aber: – XCK2: USART2 External clock. The Data Direction Register (DDRD7) controls whether theclock is output (DDRD7 set “1”) or input (DDRD7 cleared). The XCK2 pin is active only when the USART2 operates in Synchronous mode. Überseh ich was (nehme ich an) oder ist da ein Fehler im Chip?
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