vhdl process synchronous clocks

[Kus A. (Firma: 2s) (jennyzuh)]

Question about *VHDL*:

When i run this it shows to synchronous clk signals

process 
begin

tb_CLK <= '1';
tb_SPI_CLK <='1';
wait for 1 ns;
tb_CLK <= '0' ;
tb_SPI_CLK <='0';
wait for 1 ns;

end process;

When I run this it shows both signals but tb_SPI_CLK is 1 clock tick 
shifted :(
Why doesnt it work sequentially in the process ?

process 
begin

tb_CLK <= '1';
tb_SPI_CLK <=tb_CLK ;
wait for 1 ns;
tb_CLK <= '0' ;
tb_SPI_CLK <=tb_CLK ;
wait for 1 ns;

end process;

Thank you :D

[Forist (Gast)]

Kus A. schrieb:
> Question about *VHDL*:

This sound like a question about VHDL.

Perhaps https://www.mikrocontroller.net/forum/fpga-vhdl-cpld is a better 
place to ask ... ;-)

[Kus A. (Firma: 2s) (jennyzuh)]

omg i am really sorry,
i just registered here with the intention of posting it into this 
category ! now it is here xD

Thank you for your advice i will put it there

[Dussel (Gast)]

Signals are assigned at the end of a block 'same-time-assignments'.

tb_CLK <= '1';
tb_SPI_CLK <=tb_CLK ;

Assume, both signals are '0' at first. Then, at the 'wait', tb_SPI_CLK 
takes the value of tb_CLK, which is still '0' and tb_CLK is set to '1'.
The order of assignments which happen at the same time does not matter.