VHDL why is my process not sequential

[Kus A. (Firma: 2s) (jennyzuh)]

Question about *VHDL*:

When i run this it shows to synchronous clk signals:

process 
begin

tb_CLK <= '1';
tb_SPI_CLK <='1';
wait for 1 ns;
tb_CLK <= '0' ;
tb_SPI_CLK <='0';
wait for 1 ns;

end process;

------------
When I run this:
 it shows both signals but tb_SPI_CLK is 1 clock tick shifted :(
Why doesnt it work sequentially in the process ?

process 
begin

tb_CLK <= '1';
tb_SPI_CLK <=tb_CLK ;
wait for 1 ns;
tb_CLK <= '0' ;
tb_SPI_CLK <=tb_CLK ;
wait for 1 ns;

end process;

Thank you :D

[Markus F. (mfro)]

Kus A. schrieb:
> Why doesnt it work sequentially in the process ?

Because that's the way how signal assignments in VHDL processes work.

Welcome to the world of VHDL.

Best imagine that signal assignments get "collected" and not executed 
until the next wait statement (or the 'end' of the process, if there is 
no wait).

Thus you are - contrary to what you assumed - not assigning the value 
just 'written' to tb_SPI_CLK (because that 'write' does not occur any 
earlier than at the wait statement), but its previous value.

VHDL variables work like you would expect, but have other implications 
you still need to discover.