Kus A. schrieb:
> Why doesnt it work sequentially in the process ?
Because that's the way how signal assignments in VHDL processes work.
Welcome to the world of VHDL.
Best imagine that signal assignments get "collected" and not executed
until the next wait statement (or the 'end' of the process, if there is
Thus you are - contrary to what you assumed - not assigning the value
just 'written' to tb_SPI_CLK (because that 'write' does not occur any
earlier than at the wait statement), but its previous value.
VHDL variables work like you would expect, but have other implications
you still need to discover.