Hallo,
ich würde gerne eine SR Latch simulieren, um ein besseres Gefühl für
"Memory" in einem digitalen System zu bekommen.
Der Code für die SR Latch is:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 |
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4 | entity sr_latch is
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5 | port(
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6 | r, s: in std_logic;
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7 | q, q_n: out std_logic
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8 | );
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9 | end sr_latch;
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10 |
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11 | architecture struct of sr_latch is
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12 | signal x1, x2: std_logic;
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13 | begin
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14 |
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15 |
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16 | x1 <= s nor x2;
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17 | x2 <= r nor x1;
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18 |
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19 | - option 2: nand gates
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20 | -- x1 <= s nand x2;
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21 | -- x2 <= r nand x1;
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22 |
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23 | q <= x1 ;
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24 | q_n <= x2 ;
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25 | end struct ;
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Die Testbench ist:
1 | --- testbench for sequential
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2 |
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3 |
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4 | library ieee;
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5 | use ieee.std_logic_1164.all ;
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6 |
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7 |
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8 | entity latch_tb is begin
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9 | end entity latch_tb ;
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10 |
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11 |
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12 | architecture arc of latch_tb is
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13 |
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14 | component sr_latch is
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15 | port (
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16 | s : in std_logic;
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17 | r : in std_logic;
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18 | q : out std_logic ;
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19 | q_n : out std_logic
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20 | );
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21 | end component sr_latch;
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22 |
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23 | signal tb_s : std_logic;
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24 | signal tb_r : std_logic;
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25 | signal tb_q : std_logic;
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26 | signal tb_q_n : std_logic;
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27 |
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28 | signal clk : std_logic;
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29 |
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30 |
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31 | begin
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32 |
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33 | uut : sr_latch port map (
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34 | s => tb_s,
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35 | r => tb_r,
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36 | q => tb_q,
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37 | q_n => tb_q_n
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38 | );
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39 |
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40 | --- stimuli
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41 | clk_proc: process
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42 | begin
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43 |
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44 | clk <= not clk;
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45 | -- wait for clk_period/2;
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46 | wait for 5 ns;
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47 |
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48 |
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49 | if NOW > 500 ns then
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50 | wait;
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51 | end if;
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52 | end process clk_proc;
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53 |
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54 | stim_proc: process
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55 | begin
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56 | tb_s <= '1';
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57 | tb_r <= '1';
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58 |
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59 | wait for 10 ns;
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60 |
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61 | tb_s <= '1';
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62 | tb_r <= '0';
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63 |
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64 | wait for 10 ns;
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65 |
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66 | tb_s <= '1';
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67 | tb_r <= '1';
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68 |
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69 | wait for 20 ns;
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70 |
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71 | tb_s <= '0';
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72 | tb_r <= '1';
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73 |
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74 | wait for 20 ns;
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75 |
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76 | tb_s <= '1';
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77 | tb_r <= '1';
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78 |
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79 | wait for 20 ns;
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80 |
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81 | tb_s <= '1';
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82 | tb_r <= '0';
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83 |
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84 | wait for 10 ns;
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85 |
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86 | tb_s <= '0';
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87 | tb_r <= '0';
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88 |
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89 | wait for 30 ns;
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90 |
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91 | tb_s <= '1';
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92 | tb_r <= '1';
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93 |
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94 | wait for 10 ns;
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95 |
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96 | tb_s <= '1';
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97 | tb_r <= '1';
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98 |
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99 | wait;
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100 |
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101 | end process stim_proc;
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102 |
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103 | end architecture arc;
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Bei den waveforms schaue auf auf S und R und würde erwarten, dass Q und
Q_N komplementär verlaufen. Den erwarten Memory effekt sehe ich auch
nicht. Aber evt ist es auch ein Verständnisproblem. Besten Dank für eure
Hilfe.