Hey, eine Freundin und ich verzweifeln seit einigen Stunden an einer Fehlermeldung von Quartus Prime Lite: Error (suppressible): (vsim-SDF-3250) Counter_6_1200mv_85c_vhd_slow.sdo(0): Failed to find INSTANCE '/i1'. Error (suppressible): (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s). Error (suppressible): (vsim-SDF-3250) Counter_6_1200mv_85c_vhd_slow.sdo(0): Failed to find INSTANCE '/i1' Aber wir haben keine Ahnung woran das liegen könnte. Das *.bdf ist bereits die top entity, das ändert nichts am Bug. Gibt es vielleicht im Code ein Problem? Der Compiler läuft durch. Der Code:
1 | -- ADC reader: reads data from ADXL345
|
2 | |
3 | library ieee; |
4 | use ieee.std_logic_1164.all; |
5 | use ieee.numeric_std.all; |
6 | |
7 | entity g_reader is port ( |
8 | clk_50: in std_logic; -- 50 MHz clock |
9 | |
10 | reset_n : in std_logic; -- reset signal (active low) |
11 | |
12 | -- SPI interface
|
13 | CS_N : out std_logic; -- connected to chip select of g sensor |
14 | SCLK : out std_logic; -- spi clock |
15 | SDIO : inout std_logic; -- spi data (bidirectional) |
16 | |
17 | -- data output
|
18 | dataX : out std_logic_vector(12 downto 0); |
19 | dataY : out std_logic_vector(12 downto 0); |
20 | dataZ : out std_logic_vector(12 downto 0) |
21 | );
|
22 | end g_reader; |
23 | |
24 | |
25 | architecture behavior of g_reader is |
26 | signal SCLK_counter : integer := 0; -- starts clock |
27 | signal SCLK_1 : std_logic; -- 1 MHz clock |
28 | |
29 | constant half_period : time := 10 ns; |
30 | |
31 | begin
|
32 | |
33 | -- SCLK
|
34 | process(clk_50) |
35 | begin
|
36 | |
37 | if (falling_edge(clk_50)) then |
38 | |
39 | if (SCLK_counter <= 24) then |
40 | SCLK_1 <= '0'; |
41 | else
|
42 | SCLK_1 <= '1'; |
43 | end if; |
44 | |
45 | if (SCLK_counter >= 49) then |
46 | SCLK_counter <= 0; |
47 | else
|
48 | SCLK_counter <= SCLK_counter + 1; |
49 | end if; |
50 | |
51 | end if; |
52 | |
53 | end process; |
54 | |
55 | CS_N <= '0'; |
56 | SCLK <= '0'; |
57 | dataX <= "0000000000000"; |
58 | dataY <= "0000000000000"; |
59 | dataZ <= "0000000000000"; |
60 | |
61 | |
62 | end behavior; |
1 | LIBRARY ieee; |
2 | USE ieee.std_logic_1164.all; |
3 | |
4 | ENTITY g_reader_vhd_tst IS |
5 | END g_reader_vhd_tst; |
6 | ARCHITECTURE g_reader_arch OF g_reader_vhd_tst IS |
7 | -- constants
|
8 | constant half_period : time := 10 ns; |
9 | -- signals
|
10 | signal clk : std_logic := '0'; |
11 | SIGNAL clk_50 : STD_LOGIC; |
12 | SIGNAL CS_N : STD_LOGIC; |
13 | SIGNAL dataX : STD_LOGIC_VECTOR(12 DOWNTO 0); |
14 | SIGNAL dataY : STD_LOGIC_VECTOR(12 DOWNTO 0); |
15 | SIGNAL dataZ : STD_LOGIC_VECTOR(12 DOWNTO 0); |
16 | SIGNAL reset_n : STD_LOGIC; |
17 | SIGNAL SCLK : STD_LOGIC; |
18 | SIGNAL SDIO : STD_LOGIC; |
19 | COMPONENT g_reader |
20 | PORT ( |
21 | clk_50 : IN STD_LOGIC; |
22 | CS_N : OUT STD_LOGIC; |
23 | dataX : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); |
24 | dataY : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); |
25 | dataZ : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); |
26 | reset_n : IN STD_LOGIC; |
27 | SCLK : OUT STD_LOGIC; |
28 | SDIO : INOUT STD_LOGIC |
29 | );
|
30 | END COMPONENT; |
31 | BEGIN
|
32 | i1 : g_reader |
33 | PORT MAP ( |
34 | -- list connections between master ports and signals
|
35 | clk_50 => clk_50, |
36 | CS_N => CS_N, |
37 | dataX => dataX, |
38 | dataY => dataY, |
39 | dataZ => dataZ, |
40 | reset_n => reset_n, |
41 | SCLK => SCLK, |
42 | SDIO => SDIO |
43 | );
|
44 | init : PROCESS |
45 | -- variable declarations
|
46 | BEGIN
|
47 | -- code that executes only once
|
48 | WAIT; |
49 | END PROCESS init; |
50 | |
51 | clk_proc : process |
52 | begin
|
53 | clk <= not clk after half_period; |
54 | end process clk_proc; |
55 | |
56 | end g_reader_arch; |
Danke im Voraus. Grüße Jonas