ATSAMD21 Clock Configuration

NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_RWS(2);    //READ Wait States nötig für 48MHz

SYSCTRL_REGS->SYSCTRL_DFLLCTRL = SYSCTRL_DFLLCTRL_ENABLE_Msk | SYSCTRL_DFLLCTRL_ONDEMAND_Msk;   //DFLL anschalten

GCLK_REGS->GCLK_GENCTRL    = GCLK_GENCTRL_GENEN(1) | GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL48M_Val) | GCLK_GENCTRL_OE(1) | GCLK_GENCTRL_ID(0); //GLCLK0 mit DFLL48 verbinden

while(GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk);

attachPerToPin(PORTA, 27, PER_H); //zum messen

while(1);