Hi, ich verstehe nicht genau woher das X in dieser einfacher Counter TB kommt? Welche Optionen zum Debuggen gibt es? Vielen Dank TB
1 | `timescale 1 ns / 1 ps |
2 | module top_counter; |
3 | |
4 | reg clk; |
5 | |
6 | parameter N_cycles = 20; |
7 | parameter pulse_width = 5; |
8 | integer j; |
9 | |
10 | initial begin |
11 | $dumpfile("waves.vcd"); |
12 | $dumpvars(); |
13 | |
14 | end |
15 | |
16 | initial begin |
17 | clk <= 0; |
18 | for (j=0; j<N_cycles; j = j + 1) |
19 | #pulse_width clk <= ~clk; |
20 | end |
21 | |
22 | reg counter_rstn_tb; |
23 | reg counter_en_tb; |
24 | wire [1:0] counter_n_tb; |
25 | |
26 | counter #( .N(2)) u0( |
27 | .clk(clk), |
28 | .rstn(counter_rstn_tb), |
29 | .en(counter_en_tb), |
30 | .out(counter_n_tb) |
31 | ); |
32 | |
33 | initial begin |
34 | counter_en_tb <= 0; |
35 | counter_rstn_tb <= 0; |
36 | #4 counter_rstn_tb <= 1; |
37 | #8 counter_en_tb <= 0; |
38 | #10 counter_en_tb <= 1; |
39 | #20 counter_en_tb <= 1; |
40 | end |
41 | |
42 | endmodule |
Counter
1 | // https://www.chipverify.com/verilog/verilog-parameters |
2 | module counter |
3 | |
4 | #( parameter N = 2, |
5 | parameter DOWN = 0) |
6 | |
7 | ( input clk, |
8 | input rstn, |
9 | input en, |
10 | output reg [N-1:0] out); |
11 | |
12 | always @ (posedge clk) begin |
13 | if (!rstn) begin |
14 | out <= 0; |
15 | end else begin |
16 | if (en) |
17 | if (DOWN) |
18 | out <= out - 1; |
19 | else |
20 | out <= out + 1; |
21 | else |
22 | out <= out; |
23 | end |
24 | end |
25 | endmodule |