VHDL ALU ohne Libraries

library work;

use work.all;

entity ALU is

   port (

     iSrcA      : in  bit_vector;

   iSrcB      : in  bit_vector;

   iALUControl: in  bit_vector(1  downto 0);

   oALUResult : out bit_vector;

   oZero    : out bit);

end ALU;

architecture Behave of ALU is 

  signal Result : bit_vector(iSrcA'range);

  procedure addBV(signal A, B : in bit_vector(iSrcA'range);

          signal res : out bit_vector(iSrcA'range)) is

          variable Output : bit_vector(iSrcA'range);

          variable Carry : bit := '0';

  begin

    for i in iSrcA'range loop

      Output(i) := A(i) xor B(i) xor Carry;

      Carry := (A(i) and B(i)) or (Carry and (A(i) xor B(i)));

    end loop;

    res <= Output;

  end procedure;

  procedure subBV(signal A, B : in bit_vector(iSrcA'range);

          signal res : out bit_vector(iSrcA'range)) is

          signal BMinus : bit_vector(iSrcA'range);

          variable back : bit_vector(iSrcA'range);

  begin

    -- Umwandeln von Wert in B auf Zweierkomplement

    -- Dann damit addBV aufrufen

    back(BMinus'range) := (not(B(B'range)));

    BMinus <= back;

    addBV(A, BMinus, res);

  end procedure;

begin

  -- iALUControl: "00": Add, "01": Sub, "10": And, "11": Or

  process (iALUControl,iSrcA, iSrcB)

  begin

    case iALUControl is

      when "00" => -- A + B

        addBV(iSrcA, iSrcB, Result);

      when "01" => -- A - B bzw. (A + (-B))

        --subBV(iSrcA, iSrcB, Result);

      when "10" => -- A AND B

        Result <= iSrcA and iSrcB;

      when "11" => -- A OR B

        Result <= iSrcA or iSrcB;

      when others =>

        Result <= (others => '0');

    end case;

  end process;

  Output: process (Result)

  begin

    oALUResult <= Result after 15 ns;

  end process;

  ZFlag : process (Result)

  begin

    if Result = (Result'range => '0') then

      oZero <= '1' after 10 ns;

    else

      oZero <= '0' after 10 ns;

    end if;

  end process;

end architecture Behave;