1 | library work;
|
2 | use work.all;
|
3 |
|
4 | entity ALU is
|
5 | port (
|
6 | iSrcA : in bit_vector;
|
7 | iSrcB : in bit_vector;
|
8 | iALUControl: in bit_vector(1 downto 0);
|
9 | oALUResult : out bit_vector;
|
10 | oZero : out bit);
|
11 | end ALU;
|
12 |
|
13 | architecture Behave of ALU is
|
14 | signal Result : bit_vector(iSrcA'range);
|
15 | procedure addBV(signal A, B : in bit_vector(iSrcA'range);
|
16 | signal res : out bit_vector(iSrcA'range)) is
|
17 | variable Output : bit_vector(iSrcA'range);
|
18 | variable Carry : bit := '0';
|
19 | begin
|
20 | for i in iSrcA'range loop
|
21 | Output(i) := A(i) xor B(i) xor Carry;
|
22 | Carry := (A(i) and B(i)) or (Carry and (A(i) xor B(i)));
|
23 | end loop;
|
24 | res <= Output;
|
25 | end procedure;
|
26 |
|
27 | procedure subBV(signal A, B : in bit_vector(iSrcA'range);
|
28 | signal res : out bit_vector(iSrcA'range)) is
|
29 | signal BMinus : bit_vector(iSrcA'range);
|
30 | variable back : bit_vector(iSrcA'range);
|
31 | begin
|
32 | -- Umwandeln von Wert in B auf Zweierkomplement
|
33 | -- Dann damit addBV aufrufen
|
34 | back(BMinus'range) := (not(B(B'range)));
|
35 | BMinus <= back;
|
36 | addBV(A, BMinus, res);
|
37 | end procedure;
|
38 | begin
|
39 | -- iALUControl: "00": Add, "01": Sub, "10": And, "11": Or
|
40 | process (iALUControl,iSrcA, iSrcB)
|
41 | begin
|
42 | case iALUControl is
|
43 | when "00" => -- A + B
|
44 | addBV(iSrcA, iSrcB, Result);
|
45 | when "01" => -- A - B bzw. (A + (-B))
|
46 | --subBV(iSrcA, iSrcB, Result);
|
47 | when "10" => -- A AND B
|
48 | Result <= iSrcA and iSrcB;
|
49 | when "11" => -- A OR B
|
50 | Result <= iSrcA or iSrcB;
|
51 | when others =>
|
52 | Result <= (others => '0');
|
53 | end case;
|
54 | end process;
|
55 |
|
56 | Output: process (Result)
|
57 | begin
|
58 | oALUResult <= Result after 15 ns;
|
59 | end process;
|
60 |
|
61 | ZFlag : process (Result)
|
62 | begin
|
63 | if Result = (Result'range => '0') then
|
64 | oZero <= '1' after 10 ns;
|
65 | else
|
66 | oZero <= '0' after 10 ns;
|
67 | end if;
|
68 | end process;
|
69 | end architecture Behave;
|