1 | typedef struct
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2 | {
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3 | __OM union
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4 | {
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5 | __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
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6 | __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
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7 | __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
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8 | } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
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9 | uint32_t RESERVED0[864U];
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10 | __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
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11 | uint32_t RESERVED1[15U];
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12 | __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
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13 | uint32_t RESERVED2[15U];
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14 | __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
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15 | uint32_t RESERVED3[29U];
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16 | __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
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17 | __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
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18 | __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
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19 | uint32_t RESERVED4[43U];
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20 | __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
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21 | __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
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22 | uint32_t RESERVED5[6U];
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23 | __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
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24 | __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
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25 | __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
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26 | __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
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27 | __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
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28 | __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
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29 | __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
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30 | __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
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31 | __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
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32 | __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
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33 | __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
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34 | __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
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35 | } ITM_Type;
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36 |
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37 | /* ITM Trace Privilege Register Definitions */
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38 | #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
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39 | #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
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40 |
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41 | /* ITM Trace Control Register Definitions */
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42 | #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
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43 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
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44 |
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45 | #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
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46 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
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47 |
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48 | #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
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49 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
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50 |
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51 | #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
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52 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
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53 |
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54 | #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
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55 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
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56 |
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57 | #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
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58 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
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59 |
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60 | #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
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61 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
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62 |
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63 | #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
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64 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
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65 |
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66 | #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
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67 | #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
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68 |
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69 | /* ITM Integration Write Register Definitions */
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70 | #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
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71 | #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
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72 |
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73 | /* ITM Integration Read Register Definitions */
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74 | #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
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75 | #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
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76 |
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77 | /* ITM Integration Mode Control Register Definitions */
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78 | #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
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79 | #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
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80 |
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81 | /* ITM Lock Status Register Definitions */
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82 | #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
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83 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
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84 |
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85 | #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
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86 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
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87 |
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88 | #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
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89 | #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
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90 |
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91 | /* Memory mapping of Core Hardware */
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92 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
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93 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
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